Patents by Inventor Vipin Tiwari

Vipin Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PRECISE DATA TUNING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
    Publication number: 20210209456
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 8, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • OUTPUT CIRCUITS FOR AN ANALOG NEURAL MEMORY SYSTEM FOR DEEP LEARNING NEURAL NETWORK
    Publication number: 20210174185
    Abstract: Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • Precise Programming Method And Apparatus For Analog Neural Memory In An Artificial Neural Network
    Publication number: 20210142156
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 13, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • VERIFYING OR READING A CELL IN AN ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210142854
    Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
  • INPUT AND DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210098477
    Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
  • TEMPERATURE COMPENSATION IN AN ANALOG MEMORY ARRAY BY CHANGING A THRESHOLD VOLTAGE OF A SELECTED MEMORY CELL IN THE ARRAY
    Publication number: 20210090654
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 25, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210089875
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 25, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Configurable analog neural memory system for deep learning neural network
    Patent number: 10956814
    Abstract: Numerous embodiments are disclosed for a configurable hardware system for use in an analog neural memory system for a deep learning neural network. The components within the configurable hardware system that are configurable can include vector-by-matrix multiplication arrays, summer circuits, activation circuits, inputs, reference devices, neurons, and testing circuits. These devices can be configured to provide various layers or vector-by-matrix multiplication arrays of various sizes, such that the same hardware can be used in analog neural memory systems with different requirements.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 23, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • Non-volatile Memory Device With Stored Index Information
    Publication number: 20210082517
    Abstract: A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.
    Type: Application
    Filed: March 9, 2020
    Publication date: March 18, 2021
    Inventors: XIAOZHOU QIAN, XIAO YAN PI, VIPIN TIWARI
  • METHOD AND ELECTRONIC DEVICE FOR GENERATING AT LEAST ONE DATA ITEM FROM SCREENSHOT
    Publication number: 20210072880
    Abstract: A method for generating at least one data item from a screenshot and an electronic device therefor are provided. The method includes detecting, by the electronic device, a screenshot comprising content displayed on a screen of the electronic device and determining, by the electronic device, data item parameters associated with the content in the screenshot. The method also includes generating, by the electronic device, at least one data item from the screenshot based on the data item parameters, and storing, by the electronic device, the at least one data item in a file in the electronic device.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 11, 2021
    Inventors: Akhila MATHUR, Bokul BORAH, Fateh SINGH, Ranjesh VERMA, Trisha Samir MODY, Amitoj SINGH, Upendra Shenoy MANGALAPADY, Vipin TIWARI, Pradnya Dasharath PATIL
  • Current compensation block and method for programming analog neural memory in deep learning artificial neural network
    Patent number: 10943661
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: March 9, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Method and apparatus for programming analog neural memory in a deep learning artificial neural network
    Patent number: 10910061
    Abstract: Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 2, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210020255
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210019608
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • System and method for storing and retrieving multibit data in non-volatile memory using current multipliers
    Patent number: 10878897
    Abstract: A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 29, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Vipin Tiwari, Hieu Van Tran, Nhan Do
  • Method and apparatus for data refresh for analog non-volatile memory in deep learning neural network
    Patent number: 10861568
    Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Dynamic modification of programming duration based on number of cells to be programmed in analog neural memory array in deep learning artificial neural network
    Patent number: 10839907
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • TEMPERATURE COMPENSATION FOR MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM USED IN A DEEP LEARNING NEURAL NETWORK
    Publication number: 20200350015
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: HIEU VAN TRAN, STEVEN LEMKE, NHAN DO, VIPIN TIWARI, MARK REITEN
  • CONFIGURABLE INPUT BLOCKS AND OUTPUT BLOCKS AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200349421
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
    Type: Application
    Filed: June 21, 2019
    Publication date: November 5, 2020
    Inventors: Hieu Van Tran, STEPHEN TRINH, THUAN VU, STANLEY HONG, VIPIN TIWARI, MARK REITEN, NHAN DO
  • OUTPUT ARRAY NEURON CONVERSION AND CALIBRATION FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200349422
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.
    Type: Application
    Filed: June 21, 2019
    Publication date: November 5, 2020
    Inventors: Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do