Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: Exemplary embodiments include RF integrated circuit (RFIC) chips including programmable on-chip element swapping circuitry, channel swapping circuitry, and/or phase rotation circuitry to allow a common software implementation or parameter computation to be used across multiple products having different arrangements and orientations of RFICs and elements.

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Abstract: A beamforming IC operates in a transmit mode or a receive mode to respectively transmit and receive signals at different times. To that end, the beamforming IC has an element interface, a transmit branch configured to produce an output transmit signal through the element interface when in the transmit mode, and a receive branch configured to receive an input signal through the element interface when in the receive mode. The beamforming circuit also has a sampling circuit with an electrical coupling with the transmit branch. The sampling circuit is configured to sample the output transmit signal with the electrical coupling to produce a sample signal. The sampling circuit also is configured to direct the sample signal through the receive branch, which is configured to modify the phase of the sample signal to produce a modified sample signal. This modified sample signal can be used to manage the IC transmission.

Abstract: A system and method for recommending portable financial device for a payment transaction is disclosed. The method includes establishing a secure communication session with one or more external APIs during a payment transaction stage and fetching data representative of banking accounts associated with a customer from the one or more external APIs. The method further includes determining one or more transactional parameters associated with the payment transaction stage and generating an optimal score for each of the one or more portable financial devices by using Machine Learning (ML) based transaction model. The method includes identifying best suitable portable financial device with maximum optimal score and recommending the identified best suitable portable financial device for completing the payment transaction stage based on the identification.

Abstract: A system and a method for performing correction of systematic error for electronically steered antennas using on-chip programming. A plurality of channels includes a first channel. Each channel is coupled to a respective antenna element and includes a trim control circuit and a phase control circuit. The first channel is coupled to a first respective antenna element. An array calibration memory stores a plurality of phase offsets including a first phase offset. Each phase offset includes an array level calibration phase offset corresponding to a respective channel. The first phase offset corresponds to the first channel. At least one of the trim control circuit and the phase control circuit of the first channel are configured to modify phase of a first signal provided to and/or received from the first respective antenna element. The phase of the first signal is modified based at least in part on the first phase offset.

Abstract: A method of enhanced hybrid quantum-classical computing mechanism for solving optimization problems is disclosed comprising altering a value of a configuration chromosome by storing an angle memory on a shared classical memory. The angle memory corresponds to a predefined configuration chromosome. The method then generates a state vector based on the angle memory and reinitializes a quantum circuit from the state vector. Subsequently, generating at least two most probable configuration chromosome from the reinitialized quantum circuit corresponding to a superposition of qubits in a position chromosome. Subsequently selecting one of the at least two most probable configuration chromosomes for each position chromosome after evaluation by a fitness function.

Abstract: A method of enhanced hybrid quantum-classical computing mechanism for solving optimization problems is disclosed comprising altering a value of a configuration chromosome by storing an angle memory on a shared classical memory. The angle memory corresponds to a predefined configuration chromosome. The method then generates a state vector based on the angle memory and reinitializes a quantum circuit from the state vector. Subsequently, generating at least two most probable configuration chromosome from the reinitialized quantum circuit corresponding to a superposition of qubits in a position chromosome. Subsequently selecting one of the at least two most probable configuration chromosomes for each position chromosome after evaluation by a fitness function.

Abstract: A phased array system has a substrate, a plurality of elements, and a plurality of beamforming ICs. Each beamforming IC has a first set of element interfaces and a second set of element interfaces. The first set of element interfaces may be configured to be polarized in a first polarization, while the second set of element interfaces may be configured to be polarized in a second (different) polarization. Each beamforming IC has a first common interface electrically coupled with its first set of element interfaces and, in a corresponding manner, each beamforming IC also has a second common interface electrically coupled with its second set of element interfaces. The system further has an interconnect element (e.g., a circuit trace, metallization on a PCB, etc.) electrically coupling the first common interface with the second common interface of another beamforming IC.

Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.

Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Abstract: A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.

Abstract: A system and method for recommending portable financial device for a payment transaction is disclosed. The method includes establishing a secure communication session with one or more external APIs during a payment transaction stage and fetching data representative of banking accounts associated with a customer from the one or more external APIs. The method further includes determining one or more transactional parameters associated with the payment transaction stage and generating an optimal score for each of the one or more portable financial devices by using Machine Learning (ML) based transaction model. The method includes identifying best suitable portable financial device with maximum optimal score and recommending the identified best suitable portable financial device for completing the payment transaction stage based on the identification.

Abstract: A system and a method for performing correction of systematic error for electronically steered antennas using on-chip programming. A plurality of channels includes a first channel. Each channel is coupled to a respective antenna element and includes a trim control circuit and a phase control circuit. The first channel is coupled to a first respective antenna element. An array calibration memory stores a plurality of phase offsets including a first phase offset. Each phase offset includes an array level calibration phase offset corresponding to a respective channel. The first phase offset corresponds to the first channel. At least one of the trim control circuit and the phase control circuit of the first channel are configured to modify phase of a first signal provided to and/or received from the first respective antenna element. The phase of the first signal is modified based at least in part on the first phase offset.

Abstract: A phased antenna array system is provided that includes a beamforming integrated circuit and beamforming elements in communication with the integrated circuit disposed on a substrate. The beamforming integrated circuit includes multiple radio frequency (RF) signal ports. One or more of the RF signal ports includes an RF signal pad disposed between an edge of the integrated circuit and an internal RF ground pad. The RF signal pad and the internal RF ground pad of the RF signal port are oriented perpendicular with respect to the edge of the integrated circuit. Specifically, the RF signal pad has a first side disposed on or adjacent to the edge of the integrated circuit and an opposing second side that is adjacent to the internal RF ground pad. A method of controlling the phased antenna array system is also provided.

Abstract: A group of devices connected on a wireless local area network (WLAN) operate in conjunction with one another to present content. Devices in the group may be wirelessly connected via personal area network (PAN) to other devices, such as speakers. An election process is used to select a primary device. The primary device may receive content from an external source, such as a server, and distribute that content to other devices within the group via the WLAN. The parameters of that distribution, such as a content rate indicative of a bitrate of the content, transfer limit rate, and so forth are configured to preserve fidelity of the presentation while minimizing interruptions to presentation that may result due to frequency contention between the WLAN and the PAN, traffic on the WLAN, and so forth.

Abstract: A beamforming integrated circuit system is configured to optimize performance. Among other things, the system may run at a lower power than conventional integrated circuits, selectively disable branches to control certain system functions, and/or selectively position ground pads around receiving pads to enhance isolation. The system also may use a beamforming integrated circuit as a distribution circuit for a number of similar or like beamforming integrated circuits.

Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.

Abstract: A phased array includes a laminar substrate having both 1) a plurality of elements forming a patch phased array, and 2) a plurality of integrated circuits. Each integrated circuit is configured to control receipt and transmission of signals by the plurality of elements in the patch phased array. The integrated circuits also are configured to operate the phased array at one or more satellite frequencies—to transmit signals to and/or receive signals from a satellite. Each integrated circuit physically couples with one corresponding element so that incoming signals are received by the corresponding element in a first polarization, and outgoing signals are transmitted by the corresponding element in a second polarization. The phased array isolates the transmit signals from the receive signals by orienting the first and second polarizations differently.