Patents by Inventor Vipul Jain

Vipul Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190354015
    Abstract: Organic coating compositions, particularly antireflective coating compositions, are provided that comprise that comprise a component that comprises one or more uracil moieties. Preferred compositions of the invention are useful to reduce reflection of exposing radiation from a substrate back into an overcoated photoresist layer and/or function as a planarizing, conformal or via-fill layer.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Owendi Ongayi, Vipul Jain, Suzanne Coley, Anthony Zampini
  • Publication number: 20190356057
    Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Inventors: Timothy Carey, Nitin Jain, Jason Durbin, David W. Corman, Vipul Jain
  • Patent number: 10481494
    Abstract: Organic coating compositions, particularly antireflective coating compositions, are provided that comprise that comprise a component that comprises one or more parabanic acid moieties. Preferred compositions of the invention are useful to reduce reflection of exposing radiation from a substrate back into an overcoated photoresist layer and/or function as a planarizing, conformal or via-fill layer.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: November 19, 2019
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Vipul Jain, Owendi Ongayi, Suzanne Coley, Anthony Zampini
  • Publication number: 20190312359
    Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.
    Type: Application
    Filed: June 10, 2019
    Publication date: October 10, 2019
    Inventors: Kristian N. MADSEN, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
  • Publication number: 20190312330
    Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 10, 2019
    Inventors: Kristian N. Madsen, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain, Jonathan P. Comeau, Shmuel Ravid
  • Publication number: 20190274055
    Abstract: A beamforming integrated circuit system is configured to optimize performance. Among other things, the system may run at a lower power than conventional integrated circuits, selectively disable branches to control certain system functions, and/or selectively position ground pads around receiving pads to enhance isolation. The system also may use a beamforming integrated circuit as a distribution circuit for a number of similar or like beamforming integrated circuits.
    Type: Application
    Filed: December 24, 2018
    Publication date: September 5, 2019
    Inventors: Pavel Brechko, David W. Corman, Vipul Jain, Shamsun Nahar, Jason Durbin, Nitin Jain
  • Publication number: 20190236247
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for decoding Turing tests. One of the methods includes managing a database that stores data of each of a plurality of aggregation accounts; sending, for a particular account identified by one of the aggregation accounts and to a server, a request for access to account data for the particular account; receiving, from the server, data that includes a login credentials field and a Turing test challenge; extracting the Turing test challenge; providing, to an external system that is a different system from the server, the Turing test challenge; receiving, from the external system, a response to the Turing test challenge; providing, to the server, the response to the Turing test challenge; providing, to the server, the login credentials for the particular account; and receiving, from the server, account data for the particular account.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Vipul Jain, Ritu Bhandari, Apoorv Awasthi
  • Patent number: 10365562
    Abstract: Organic coating compositions, particularly antireflective coating compositions, are provided that comprise that comprise a component that comprises one or more uracil moieties. Preferred compositions of the invention are useful to reduce reflection of exposing radiation from a substrate back into an overcoated photoresist layer and/or function as a planarizing, conformal or via-fill layer.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 30, 2019
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Owendi Ongayi, Vipul Jain, Suzanne Coley, Anthony Zampini
  • Patent number: 10320093
    Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 11, 2019
    Assignee: ANOKIWAVE, INC.
    Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
  • Patent number: 10303862
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for decoding Turing tests. One of the methods includes managing a database that stores data of each of a plurality of aggregation accounts; sending, for a particular account identified by one of the aggregation accounts and to a server, a request for access to account data for the particular account; receiving, from the server, data that includes a login credentials field and a Turing test challenge; extracting the Turing test challenge; providing, to an external system that is a different system from the server, the Turing test challenge; receiving, from the external system, a response to the Turing test challenge; providing, to the server, the response to the Turing test challenge; providing, to the server, the login credentials for the particular account; and receiving, from the server, account data for the particular account.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: May 28, 2019
    Assignee: Yodlee, Inc.
    Inventors: Vipul Jain, Ritu Bhandari, Apoorv Awasthi
  • Patent number: 10290951
    Abstract: A laminar phased array has a plurality of receive elements and dual transmit/receive elements supported on a substrate. The plurality of receive elements and dual transmit/receive elements form a patch array across the substrate. As such, the receive elements and dual transmit/receive elements form an array of patch antennas on the substrate. The phased array also has a plurality of integrated circuits supported on the substrate. At least a first set of the plurality of integrated circuits is configured to control receipt of signals by the receive elements. In a corresponding manner, at least a second set of the plurality of integrated circuits is configured to control receipt and transmission of signals by the dual transmit/receive elements.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 14, 2019
    Assignee: ANOKIWAVE, INC.
    Inventors: Vipul Jain, Nitin Jain, David W. Corman
  • Publication number: 20190132035
    Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 2, 2019
    Inventors: Robert J. McMorrow, Vipul Jain, Wade C. Allen, David W. Corman, Robert Ian Gresham, Kristian N. Madsen, Nitin Jain
  • Patent number: 10263650
    Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 16, 2019
    Assignee: ANOKIWAVE, INC.
    Inventors: David Warren Corman, Robert McMorrow, Andrew Street, Vipul Jain, Kristian Madsen, Robert Ian Gresham, Jonathan Comeau, Gaurav Menon, Nitin Jain
  • Patent number: 10251079
    Abstract: Cloud-based management of cell-based test systems is described. For example, at a server that is communicatively coupled to a cell-based test system via a network (that is, in the cloud), a test case from a test case library is selected and accessed. The test case is selected according to the type of user equipment to be tested at the cell-based test system. The test case is sent from the server over the network to the cell-based test system. The cell-based test system can automatically perform the test case on the user equipment. Results from performing the test case on the user equipment are then stored on the cloud; that is, the test results are received at the server from the cell-based test system over the network and stored at the server. A report based on the test results can be prepared and stored on the server (in the cloud).
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 2, 2019
    Assignee: W2BI, INC.
    Inventors: Dinesh Doshi, Amit Kucheriya, Liqun Liu, Vipul Jain, Derek Diperna, Mark Elston, Ira Leventhal
  • Patent number: 10200098
    Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: February 5, 2019
    Assignee: Anokiwave, Inc.
    Inventors: Robert J. McMorrow, Vipul Jain, Wade C. Allen, David W. Corman, Robert Ian Gresham, Kristian N. Madsen, Nitin Jain
  • Patent number: 10158552
    Abstract: To test user equipment at a cell-based test system, a type of user equipment to be tested is determined. A device profile for the type of the user equipment to be tested is accessed. The device profile includes, for example, a test script that can be used to control the user equipment during the testing. A test of the user equipment is performed at the cell-based test system. During the test, the user equipment is controlled according to the device profile in response to the software executing on a computer system.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 18, 2018
    Assignee: W2BI, INC.
    Inventors: Dinesh Doshi, Mark Elston, Derek Diperna, Vipul Jain, Liqun Liu, Amit Kucheriya, Ira Leventhal
  • Patent number: 10133179
    Abstract: A pattern treatment method, comprising: (a) providing a semiconductor substrate comprising a patterned feature on a surface thereof; (b) applying a pattern treatment composition to the patterned feature, wherein the pattern treatment composition comprises: a block copolymer and an organic solvent, wherein the block copolymer comprises: (i) a first block comprising a first unit formed from 4-vinyl-pyridine, and (ii) a second block comprising a first unit formed from a vinyl aromatic monomer; and (c) removing residual pattern shrink composition from the substrate, leaving a coating of the block copolymer over the surface of the patterned feature, thereby providing a reduced pattern spacing as compared with a pattern spacing of the patterned feature prior to coating the pattern treatment composition. The methods find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 20, 2018
    Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Jin Wuk Sung, Mingqi Li, Jong Keun Park, Joshua A. Kaitz, Vipul Jain, Chunyi Wu, Phillip D. Hustad
  • Publication number: 20180287266
    Abstract: Illustrative embodiments significantly improve RF isolation in a packaged integrated circuit by separating the pins/pads associated with multiple RF channels from one another and also from pins/pads associated with digital circuits. Specifically, in certain exemplary embodiments, the integrated circuit is configured with the pins/pad for the digital circuits on a first edge of the chip, the pins/pads for common RF signals on a second edge of the chip opposite the first edge, and the pins/pads for the individual RF channels on third and fourth edges of the chip. The pins/pads associated with each RF channel may include multiple pins/pads (an “RF group”) and may have a central RF pin/pad with a ground pin/pad on each side of the central RF pin/pad. One or more ground pins/pads may be placed between adjacent RF groups on a given edge of the chip.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 4, 2018
    Inventors: Kristian N. Madsen, Vipul Jain, Amir Esmaili, Chad Cookinham, Noyan Kinayman, Shamsun Nahar, David W. Corman, Nitin Jain
  • Publication number: 20180234121
    Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.
    Type: Application
    Filed: January 2, 2018
    Publication date: August 16, 2018
    Inventors: David Warren Corman, Robert McMorrow, Andrew Street, Vipul Jain, Kristian Madsen, Robert Ian Gresham, Jonathan Comeau, Gaurav Menon, Nitin Jain
  • Patent number: 10042255
    Abstract: Block copolymers comprise a first block comprising an alternating copolymer, and a second block comprising a unit comprising a hydrogen acceptor. The block copolymers find particular use in pattern shrink compositions and methods in semiconductor device manufacture for the provision of high resolution patterns.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 7, 2018
    Assignees: Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC
    Inventors: Huaxing Zhou, Vipul Jain, Jin Wuk Sung, Peter Trefonas, III, Phillip D. Hustad, Mingqi Li