Patents by Inventor Viraj Patwardhan

Viraj Patwardhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200214545
    Abstract: A binocular image capture device includes a plurality of stacked circuit boards, a front-facing dual image sensor mounted to a first circuit board of the plurality of stacked circuit boards, and signal conditioning electronics mounted to one or more of the plurality of stacked circuit boards and coupled to receive electrical signals generated by the dual image sensor. The dual image sensor is enclosed in a hermetic housing. In some examples, the hermetic housing may be formed by the first circuit board, a transition ring secured to the first circuit board, and an optics mount secured to the transition ring. In some examples, the hermetic housing may be formed using materials having matching coefficients of thermal expansion. In some examples, the binocular image capture device is enclosed by a shaft, the plurality of stacked circuit boards being stacked along a length of the shaft.
    Type: Application
    Filed: February 11, 2020
    Publication date: July 9, 2020
    Inventors: Viraj A. Patwardhan, John A Barton, Mathew Clopp, John E. Sell
  • Patent number: 10575714
    Abstract: A binocular image capture device includes a plurality of stacked circuit boards, a front-facing dual image sensor mounted to a first circuit board of the plurality of stacked circuit boards, and signal conditioning electronics mounted to one or more of the plurality of stacked circuit boards and coupled to receive electrical signals generated by the dual image sensor. The dual image sensor is enclosed in a hermetic housing. In some examples, the hermetic housing may be formed by the first circuit board, a transition ring secured to the first circuit board, and an optics mount secured to the transition ring. In some examples, the hermetic housing may be formed using materials having matching coefficients of thermal expansion. In some examples, the binocular image capture device is enclosed by a shaft, the plurality of stacked circuit boards being stacked along a length of the shaft.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 3, 2020
    Assignee: INTUITIVE SURGICAL OPERATIONS, INC.
    Inventors: Viraj A. Patwardhan, John A Barton, Mathew Clopp, John E. Sell
  • Publication number: 20190150716
    Abstract: A binocular image capture device includes a plurality of stacked circuit boards, a front-facing dual image sensor mounted to a first circuit board of the plurality of stacked circuit boards, and signal conditioning electronics mounted to one or more of the plurality of stacked circuit boards and coupled to receive electrical signals generated by the dual image sensor. The dual image sensor is enclosed in a hermetic housing. In some examples, the hermetic housing may be formed by the first circuit board, a transition ring secured to the first circuit board, and an optics mount secured to the transition ring. In some examples, the hermetic housing may be formed using materials having matching coefficients of thermal expansion. In some examples, the binocular image capture device is enclosed by a shaft, the plurality of stacked circuit boards being stacked along a length of the shaft.
    Type: Application
    Filed: May 15, 2017
    Publication date: May 23, 2019
    Inventors: Viraj A. Patwardhan, John A. Barton, Mathew Clopp, John E. Sell
  • Patent number: 8324602
    Abstract: An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Patent number: 8232541
    Abstract: An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: July 31, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Publication number: 20110024910
    Abstract: Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 3, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shahram MOSTAFAZADEH, Viraj A. PATWARDHAN
  • Patent number: 7838991
    Abstract: Improved protective metallization is described for bumped copper-top semiconductor chips. The semiconductor device includes a top wafer fabrication passivation layer with openings through which contact pads are exposed. A patterned copper layer is formed over the passivation layer and is electrically coupled to the contact pads through the openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies the patterned copper layer and cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. An aluminum metallization layer overlies the titanium metallization layer. An electrically insulating protective layer overlies the aluminum metallization and passivation layers. The protective layer includes openings in which underbump metallization stacks are formed. Each underbump metallization stack electrically connects to the aluminum metallization layer through an opening in the protective layer.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: November 23, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Viraj Patwardhan
  • Publication number: 20100259766
    Abstract: Provided herein are optical sensor devices, methods for making the same, and systems including the same. An optical sensor device, according to an embodiment, includes a light detector die and a light source die attached to the same or different die attachment substrates so that there is a space between the light source die and the light detector die. A light transmissive material covers the light detector die, the light source die and at least a portion of the space between the light detector die and the light source die. A groove is formed (e.g., saw, blade or laser cut, or cast) in the light transmissive material between the light detector die and the light source die, and an opaque material is put within the groove to provide a light barrier between the light detector die and the light source die.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Publication number: 20100258710
    Abstract: An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device.
    Type: Application
    Filed: December 21, 2009
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Publication number: 20100258712
    Abstract: An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
  • Patent number: 7674702
    Abstract: A polymer stencil is applied to the active surface of a wafer. The stencil has openings that at least partially overlay associated metallization pads on the wafer and divider strips positioned between adjacent openings. The divider strips are arranged to overlay portions of associated metallization pads so that at least two adjacent openings overlay portions of each metallization pad. After the stencil has been positioned, a solder paste is applied to the stencil openings. The solder paste may then be reflowed with the polymer stencil remaining in place. The solder naturally creeps under the stencil so that unitary solder bumps are formed on each metallization pad. The described methods and arrangements can be used to create low profile solder bumps that are not attainable using conventional solder bump formation techniques.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: March 9, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Viraj Patwardhan, Nikhil V. Kelkar
  • Patent number: 7642175
    Abstract: A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: January 5, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Lian Hee Tan, Nikhil Vishwanath Kelkar
  • Patent number: 7629246
    Abstract: A Micro SMDxt package is provided that configured for mounting to a circuit board. The SMDxt package includes a silicon-based IC having an array of contact pads on one side of thereof, and a die electrically attached to the silicon-based IC. A plurality of solder balls is included, each of which has a polymeric core surrounded by a metallic shell that in turn is surrounded by a layer of solder material. Further, each solder ball is positioned in contact with a corresponding contact pad of the package. An intertwined intermetallic fusion layer is formed through the fusion between material components of the contact pads and the solder material, via heat treatment. The intermetallic fusion extends between and from an outer surface of the metallic shell of each solder to an outer surface of a corresponding contact pad to form a high strength intermetallic solder joint therebetween.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 8, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Viraj Patwardhan, Hau Nguyen
  • Publication number: 20090057897
    Abstract: A Micro SMDxt package is provided that configured for mounting to a circuit board. The SMDxt package includes a silicon-based IC having an array of contact pads on one side of thereof, and a die electrically attached to the silicon-based IC. A plurality of solder balls is included, each of which has a polymeric core surrounded by a metallic shell that in turn is surrounded by a layer of solder material. Further, each solder ball is positioned in contact with a corresponding contact pad of the package. An intertwined intermetallic fusion layer is formed through the fusion between material components of the contact pads and the solder material, via heat treatment. The intermetallic fusion extends between and from an outer surface of the metallic shell of each solder to an outer surface of a corresponding contact pad to form a high strength intermetallic solder joint therebetween.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Viraj Patwardhan, Hau Nguyen
  • Patent number: 7423337
    Abstract: An apparatus and method for increasing integrated circuit device package reliability is disclosed. According to one embodiment of the present invention, a support coating is added to a wafer after solder bumps have been added but prior to dicing. This support coating or underfill layer provides added strength to the eventual reflowed solder connections, such that the operational lifetime of these connections is increased with respect to failure due to temperature cycling.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Hau Nguyen, Nikhil K. Kelkar, Shahram Mostafazadeh
  • Patent number: 7413927
    Abstract: An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 19, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Hau T. Nguyen, Nikhil Kelkar
  • Patent number: 7375431
    Abstract: A polymer stencil is applied to the active surface of a wafer. The stencil has openings that at least partially overlay associated metallization pads on the wafer and divider strips positioned between adjacent openings. The divider strips are arranged to overlay portions of associated metallization pads so that at least two adjacent openings overlay portions of each metallization pad. After the stencil has been positioned, a solder paste is applied to the stencil openings. The solder paste may then be reflowed with the polymer stencil remaining in place. The solder naturally creeps under the stencil so that unitary solder bumps are formed on each metallization pad. The described methods and arrangements can be used to create low profile solder bumps that are not attainable using conventional solder bump formation techniques.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: May 20, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Viraj Patwardhan, Nikhil V. Kelkar
  • Patent number: 7301222
    Abstract: An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: November 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Hau T. Nguyen, Nikhil Kelkar
  • Patent number: 7253078
    Abstract: An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: August 7, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hau T. Nguyen, Viraj A. Patwardhan, Nikhil Kelkar, Shahram Mostafazadeh
  • Patent number: 7135385
    Abstract: A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer is affixed to the back surface of the wafer. Thereafter, the mount layer of the backcoat/mount tape is removed while leaving the backcoat layer affixed to the back surface of the integrated circuit devices. In some embodiments, the mount layer includes an ultraviolet (UV) sensitive adhesive material that releases when exposed to UV light. The described arrangements can be used to form integrated circuits having very thin protective backcoatings. By way of example, opaque protective films having thickness in the range of 5 to 50 microns are readily obtainable.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: November 14, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Lian Hee Tan, Nikhil Vishwanath Kelkar