Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.

Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.

Abstract: A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.

Abstract: A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit.

Abstract: A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.

Abstract: A microprogrammed commercial instruction processor in a data processing system includes a bank of switches coupled to a multitapped delay line for selecting delay line signals for setting the basic clock timing. Another of the switches when activated conditions the commercial instruction processor so that when it is reset a special clock setting firmware loop is entered. The loop provides an uninterrupted succession of clock pulses which allows one to adjust the basic clock timing within specification.

Abstract: A data processing system which includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal, as well as the length and position of the most significant decimal digit in a main memory word, are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory, high order word first or low order word first, the number of double words in the operand and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor.

Abstract: A data processing system includes a commercial instruction processor (CIP) for executing decimal arithmetic instructions. The operands processed by the CIP include packed decimal and string decimal operands. The decimal arithmetic instruction includes descriptors for describing the characteristics of the operands. A register coupled to an arithmetic logic unit stores double words of the operands which are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory. The read only memory output write signals select the decimal digit, byte or double word positions of the register for writing.

Abstract: A microprogrammed controlled commercial instruction processor coupled to a common bus executes a diagnostic microprogram to check the data path of the common bus interface registers and their associated internal registers. Decoded bits of a predetermined microword of the diagnostic microprogram generate a signal which transfers a predetermined data word containing a plurality of bytes stored in a first of the internal registers sequentially through the interface registers to a second of the internal registers during one microword cycle. Apparatus generates bad parity for selected bytes. Subsequent microwords compare the contents of the first and second internal registers and verify the detection of the "bad" parity.

Abstract: A data processor performs a decimal multiply operation using apparatus including a register for storing multiplier decimal digits, a register for storing a multiplicand operand of decimal digits, a register for storing partial products and arithmetic logic units, and a read only memory for storing the units and tens product digits. The multiplier digit and a selected multiplicand digit are applied to the address terminals of the read only memory. On successive cycles, the units product digit and the tens product digit are added respectively to selected partial product digits and the sum replaces the selected partial product digits.

Abstract: A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.

Abstract: An alphanumeric search apparatus wherein a plurality of search indicia stored in a first operand and a plurality of elements stored in a second operand are operated upon by a data processing system to determine by means of search or verify operations whether any of the elements included in the second operand correspond to any one of the indicia included in the first operand. The second operand may be arranged in a sequential string of elements or in an array or table of elements and a search is conducted by comparing each element sequentially with all the search indicia and by so processing the elements until a match is found. A verify procedure is conducted by comparing each element with the search indicia to verify that there is a counterpart for each search element in the list of search indicia. For a search procedure, an output is generated indicating the storage locations within their respective operands of the search indicia and the element which produced the match.

Abstract: A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from a descriptor word of the instruction, and signals indicating the present decimal digit position being processed to generate signals indicating next decimal digit position to be processed.

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract: In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.

Abstract: A data processing system having a control store storing firmware words for controlling the system, logic for executing logical operations on input data, including the performing of a first and second data processing routine, and apparatus for addressing the control store to access selected firmware words to control the execution of desired logical operations on the input data. The system operates in a particular mode of control to suspend the operation of the first routine in order to execute the second routine whereby the logical apparatus includes a register for saving a return address associated with the last instruction of the first routine. When the system terminates the second routine and restores the first routine to operation, the contents of the save register are employed, with the lowest order bit thereof inverted, to access the control store to fetch the firmware word used to reenter the first routine.

Abstract: Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.

Abstract: Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.

Abstract: Information from a main data processor is transferred to an auxiliary data processor of the system and is stored in a control file which may be addressed by either a firmware word from a control store or by use of the function code received in an instruction from the main processor. Information in such control file is used for the purpose of addressing main memory. The address for main memory may be incremented or decremented simultaneously as operands are being fetched from main memory for execution.

Abstract: Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logic unit, the type of operation being performed and whether the binary arithmetic logic unit produced a carry as a result of its arithmetic operation on such operands.