Patents by Inventor Virgile Javerliac

Virgile Javerliac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304529
    Abstract: A circuit for reading a programmed resistive state of resistive elements of a resistive memory, wherein each resistive element may be programmed to be in a first or a second resistive state, wherein the circuit includes a current integrator suitable for integrating a difference in current between a reading current flowing through a first of the resistive elements and a reference current.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 28, 2019
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Salim Renane, Pierre Paoli, Virgile Javerliac
  • Patent number: 9653135
    Abstract: A multi-port memory cell including: first and second magnetoresistive elements, each of which is programmable so as to adopt at least two resistive states, in which: the first magnetoresistive element is coupled with a first output line and is programmable by the direction of a current which is passed through same; and the second magnetoresistive element is coupled with a second output line and is arranged so as to be magnetically coupled with the first magnetoresistive element, the second magnetoresistive element being programmable by a magnetic field generated by the first magnetoresistive element.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: May 16, 2017
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Fabrice Bernard-Granger, Virgile Javerliac
  • Publication number: 20170131910
    Abstract: A register including: a plurality of volatile memory cells each having a first input and an output, the volatile memory cells being coupled in series with each other via their first inputs and outputs; a non-volatile memory comprising a plurality of non-volatile memory cells; and one or more serial connections adapted to perform at least one of: serially supply data to be written to the non-volatile memory from a last or another of the volatile memory cells to the non-volatile memory during a back-up operation of data stored by the volatile memory cells; and serially supply data read from the non-volatile memory to a first of the volatile memory cells during a restoration operation of the data stored by the volatile memory cells.
    Type: Application
    Filed: June 8, 2015
    Publication date: May 11, 2017
    Applicants: Commissariat à I'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Pierre Paoli, Christophe Layer, Virgile Javerliac, Jean-Pierre Nozieres
  • Patent number: 9640257
    Abstract: A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 2, 2017
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Virgile Javerliac, Christophe Layer
  • Patent number: 9620212
    Abstract: A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: April 11, 2017
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Virgile Javerliac, Christophe Layer
  • Publication number: 20160336052
    Abstract: A multi-port memory cell including: first and second magnetoresistive elements, each of which is programmable so as to adopt at least two resistive states, in which: the first magnetoresistive element is coupled with a first output line and is programmable by the direction of a current which is passed through same; and the second magnetoresistive element is coupled with a second output line and is arranged so as to be magnetically coupled with the first magnetoresistive element, the second magnetoresistive element being programmable by a magnetic field generated by the first magnetoresistive element.
    Type: Application
    Filed: December 15, 2014
    Publication date: November 17, 2016
    Inventors: Fabrice Bernard-Granger, Virgile Javerliac
  • Publication number: 20160329098
    Abstract: A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.
    Type: Application
    Filed: January 7, 2015
    Publication date: November 10, 2016
    Applicants: Commissariat à I'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Virgile Javerliac, Christophe Layer
  • Publication number: 20160329100
    Abstract: A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.
    Type: Application
    Filed: January 7, 2015
    Publication date: November 10, 2016
    Applicants: Commissariat à L'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Virgile Javerliac, Christophe Layer
  • Patent number: 9311994
    Abstract: The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: April 12, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, Centre National de la Recherche Scientifique
    Inventors: Grégory Di Pendina, Virgile Javerliac
  • Patent number: 8941428
    Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: January 27, 2015
    Assignee: ARM Limited
    Inventors: Virgile Javerliac, Yannick Marc Nevers, Laurent Christian Sibuet, Selma Laabidi
  • Publication number: 20150009744
    Abstract: The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration.
    Type: Application
    Filed: July 4, 2014
    Publication date: January 8, 2015
    Inventors: Grégory Di Pendina, Virgile Javerliac
  • Patent number: 8902643
    Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 2, 2014
    Assignee: Crocus Technology Inc.
    Inventors: Neal Berger, Jean-Pierre Nozieres, Virgile Javerliac
  • Patent number: 8885429
    Abstract: A memory device including an array of memory cells arranged as a plurality of rows and columns. Write circuitry then controls a voltage level of the associated at least one bit line for each of the addressed memory cells to cause write data to be written into the addressed memory cells. In the presence of an asserted erase signal, a decoder circuitry's operation is modified such that it issues, independently of the clock signal, an asserted word line signal on the word line associated with each row in a predetermined erase region of the array. Further, the write circuitry's operation is modified so that it controls the voltage level of the associated at least one bit line for each memory cell in the predetermined erase region, in order to cause erase write data to be written into the memory cells of the predetermined erase region.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: November 11, 2014
    Assignee: ARM Limited
    Inventors: Nicolaas Klarinus Johannes Van Winkelhoff, Pierre Lemarchand, Bastien Jean Claude Aghetti, Virgile Javerliac
  • Publication number: 20140218089
    Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: ARM LIMITED
    Inventors: Virgile JAVERLIAC, Yannick Marc NEVERS, Laurent Christian SIBUET, Selma LAABIDI
  • Publication number: 20140125392
    Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: ARM LIMITED
    Inventors: Virgile JAVERLIAC, Yannick Marc NEVERS, Laurent Christian SIBUET, Selma LAABIDI
  • Patent number: 8504961
    Abstract: An integrated circuit includes processing circuitry that includes a plurality of critical path circuits. These critical path circuits include variable delay circuits which add an additional delay in to a path delay through each of the critical path circuits so as to adjust the path delay to match a target path delay. Variable delay circuit includes a tank capacitor which is charged or discharged to generate a control voltage. This control voltage serves to control a power supply voltage fed to an inverter chain. Variation in the power supply voltage of the inverter chain adjust the propagation speed of a processing signal through the inverter chain and accordingly adjusts the additional delay imposed by the variable delay circuit.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: August 6, 2013
    Assignee: ARM Limited
    Inventor: Virgile Javerliac
  • Patent number: 8344758
    Abstract: A device for performing a “logic function” consisting of a magnetic structure including at least a first magnetoresistive stack including a first ferromagnetic layer and a second ferromagnetic layer separated by a non-ferromagnetic interlayer and at least one first line of current situated in the vicinity of the first magnetoresistive stack and generating in the vicinity of the first stack a magnetic field when an electric current passes through it. The first line includes at least two current input points so that two currents can be added together in the first line, with the sum of the two currents being determined by the logic function.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 1, 2013
    Assignees: Commissariat á l'énergie atomique et aux energies alternatives, Centre national de la recherche scientifique
    Inventors: Virgile Javerliac, Guillaume Prenat
  • Patent number: 8289765
    Abstract: A magnetic random access memory (MRAM) cell with a thermally assisted writing procedure comprising a magnetic tunnel junction formed from a magnetic storage layer, a reference layer, and an insulating layer inserted between the reference layer and the storage layer; and a first strap portion laterally connecting one end of the magnetic tunnel junction to a first selection transistor; wherein the cell further comprises a second strap portion extending opposite to the first strap portion and connecting laterally said one end of the magnetic tunnel junction to a second selection transistor, and in that said first and second strap portions being adapted for passing a portion of current via the first and second selection transistors. The disclosed cell has lower power consumption than conventional MRAM cells.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: October 16, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Erwan Gapihan, Mourad El Baraji
  • Patent number: 8228702
    Abstract: The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively connected to one extremity of the first and second straps; a first and second current lines; and a conductive line electrically connecting in series the first and second magnetic tunnel junctions at their ends opposed to the ones connecting the first and second straps. The cell disclosed herein has smaller size and can be advantageously used in memory devices having a high cell density array.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Mourad El Baraji
  • Patent number: 8228703
    Abstract: A method for writing a magnetic random access memory-based ternary content addressable memory cell comprising a first magnetic tunnel junction being formed from a storage layer, a sense layer having a magnetization direction adjustable relative to the magnetization of the storage layer, and an insulating layer between the storage and sense layers; a sense line coupled with the storage layer; a first field line and a second field line, and the first field line being orthogonal to the second field line; comprising: providing a first write data to said storage layer via the second field line to store a first stored data with a high or low logic state; characterized in that, the method further comprises providing the first write data to said storage layer via the first field line to store the first stored data with a masked logic state.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 24, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Mourad El Baraji