Patents by Inventor Vishal P. Trivedi

Vishal P. Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105678
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 11, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Patent number: 9106179
    Abstract: Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes an active-circuit arrangement that facilitates generation of an oscillating signal, and a resonator arrangement capacitively coupled to the active-circuit arrangement to influence an oscillation frequency of the oscillating signal based on a difference between a first control voltage and a second control voltage.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: August 11, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Vishal P. Trivedi, Kun-Hin To
  • Patent number: 9099957
    Abstract: Apparatus are provided for voltage-controlled oscillators (VCOs) and related systems. An exemplary VCO includes an active-circuit arrangement employing cross-coupled amplifying elements that facilitate generation of an oscillating signal, plus a resonator arrangement capacitively coupled via resonator terminals to primary terminals of the active-circuit arrangement, to influence an oscillation frequency of the oscillating signal based on a difference between control voltages applied to first and second control terminals of the resonator arrangement. When employing bipolar amplifying elements their control terminals are cross-coupled to the opposing resonator terminals. VCO output may be taken from the primary terminals or from the resonator terminals.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 4, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Vishal P. Trivedi, Kun-Hin To
  • Patent number: 9099445
    Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal P. Trivedi, Jay P. John
  • Patent number: 9070786
    Abstract: A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: June 30, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventor: Vishal P. Trivedi
  • Publication number: 20150056767
    Abstract: A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Inventor: VISHAL P. TRIVEDI
  • Patent number: 8912569
    Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current 56 from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current 56 is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Publication number: 20140131772
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Inventors: JAY P. JOHN, JAMES A. KIRCHGESSNER, VISHAL P. TRIVEDI
  • Patent number: 8664698
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: March 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Publication number: 20140027817
    Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current (69) from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current (69) is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Vishal P. Trivedi
  • Patent number: 8629732
    Abstract: Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes a first variable capacitance element, a second variable capacitance element coupled between the first control voltage node and the third node, and an inductive element coupled between the variable capacitance elements to provide an inductance between the variable capacitance elements at an oscillation frequency of an oscillating signal at an output node. The first variable capacitance element is coupled between a first control voltage node and the output node, the second variable capacitance element is coupled to the first control voltage node, and a second inductive element is coupled between the second variable capacitance element and a second control voltage node.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal P. Trivedi, Kun-Hin To
  • Publication number: 20140001650
    Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 2, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vishal P. Trivedi, Jay P. John
  • Patent number: 8530347
    Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal P. Trivedi, Jay P. John
  • Patent number: 8498140
    Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: July 30, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Leo Mathew, Michael Sadd, Vishal P. Trivedi
  • Patent number: 8461012
    Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Publication number: 20130082790
    Abstract: Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes a first variable capacitance element, a second variable capacitance element coupled between the first control voltage node and the third node, and an inductive element coupled between the variable capacitance elements to provide an inductance between the variable capacitance elements at an oscillation frequency of an oscillating signal at an output node. The first variable capacitance element is coupled between a first control voltage node and the output node, the second variable capacitance element is coupled to the first control voltage node, and a second inductive element is coupled between the second variable capacitance element and a second control voltage node.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vishal P. Trivedi, Kun-Hin To
  • Publication number: 20120319787
    Abstract: An oscillator circuit is provided for generating an oscillating signal. The oscillator circuit includes a transistor circuit, a resonator circuit, and first and second transmission line open stubs. The transistor circuit is coupled to a first node and a second node of the oscillator circuit. The transistor circuit is for facilitating oscillation of the oscillating signal. The resonator circuit is coupled to the first node and the second node, and includes an inductance and a capacitance. The first and second transmission line open stubs are coupled to the first and second nodes, respectively. The first and second transmission line open stubs have a length substantially equal to a quarter wavelength of a second harmonic of the oscillating signal, and are for removing the second harmonic from the oscillating signal. In another embodiment, first and second half wave AC shorted stubs are used to remove the second harmonic from the oscillating signal.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Inventors: VISHAL P. TRIVEDI, KUN-HIN TO
  • Patent number: 8324064
    Abstract: Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 4, 2012
    Assignee: Freescale Semiconductors, Inc.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Publication number: 20120235757
    Abstract: Apparatus are provided for voltage-controlled oscillators (VCOs) and related systems. An exemplary VCO includes an active-circuit arrangement employing cross-coupled amplifying elements that facilitate generation of an oscillating signal, plus a resonator arrangement capacitively coupled via resonator terminals to primary terminals of the active-circuit arrangement, to influence an oscillation frequency of the oscillating signal based on a difference between control voltages applied to first and second control terminals of the resonator arrangement. When employing bipolar amplifying elements their control terminals are cross-coupled to the opposing resonator terminals. VCO output may be taken from the primary terminals or from the resonator terminals.
    Type: Application
    Filed: May 31, 2012
    Publication date: September 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vishal P. Trivedi, Kun-Hin To
  • Publication number: 20120235758
    Abstract: Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes an active-circuit arrangement that facilitates generation of an oscillating signal, and a resonator arrangement capacitively coupled to the active-circuit arrangement to influence an oscillation frequency of the oscillating signal based on a difference between a first control voltage and a second control voltage.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vishal P. TRIVEDI, Kun-Hin TO