Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract: A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a silicon wafer, as well as ablation processes. A first laser generates periodic pulses of radiation along a beam path directed at the target material. Similarly, at least one additional laser generates periodic pulses. A beam aligner redirects the beam path of the at least one additional laser, such that the beam from the at least one additional laser is directed at the target along a path colinear with the first laser's beam path. As a result, all the lasers are directed at the target along the same combined beam path. The periodic pulses of the at least one additional laser are delayed relative to the first laser such that multiple pulses impinge on the target within a single pulse cycle of any given laser.

Abstract: A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the reaction chamber. A rough ruthenium layer may be deposited on the surface of the substrate assembly at a rate of about 100 ?/minute to about 500 ?/minute using the ruthenium-containing precursor. Further, a rough ruthenium oxide layer may be formed by providing a ruthenium-containing precursor and an oxygen-containing precursor into the reaction chamber to deposit the rough ruthenium oxide layer on the surface of the substrate assembly at a rate of about 100 ?/minute to about 1200 ?/minute. An anneal of the layers may be performed to further increase the roughness. In addition, conductive structures including a rough ruthenium layer or a rough ruthenium oxide layer are provided. Such layers may be used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form conductive structures.

Abstract: Polishing pads used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such polishing pads. In one aspect of the invention, a polishing pad for planarizing microelectronic-device substrate assemblies has a backing member including a first surface and a second surface, a plurality of pattern elements distributed over the first surface of the backing member, and a hard cover layer over the pattern elements. The pattern elements define a plurality of contour surfaces projecting away from the first surface of the backing member. The cover layer at least substantially conforms to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member. The hard nodules define abrasive elements to contact and abrade material from a microelectronic-device substrate assembly. As such, the cover layer defines at least a portion of a planarizing surface of the polishing pad.

Abstract: The present invention provides a processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube coupled between the remote activation region and a semiconductor processing chamber, and a source of photo-energy for maintaining activation of the active species or providing photo-energy for a non-plasma species during transfer through the transparent tube to the processing chamber. The source of photo-energy preferably includes an array of UV lamps. Additional UV lamps may also be used to further sustain active species and assist processes by providing additional in-situ energy through a transparent window of the processing chamber. The system can be utilized for processes such as layer-by-layer annealing and deposition and also removal of contaminants from deposited layers.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the structure. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of structure materials and oxidation methods. Additional embodiments are disclosed and claimed.

Abstract: The invention includes methods of forming capacitors and capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the apparatus may include a species analyzer that receives a slurry resulting from the planarization process and analyzes the slurry to determine the presence of an endpointing material implanted beneath the surface of the microelectronic substrate. The species analyzer may include a mass spectrometer or a spectrum analyzer. In another embodiment, the apparatus may include a radiation source that directs impinging radiation toward the microelectronic substrate, exciting atoms of the substrate, which in turn produce an emitted radiation. A radiation detector is positioned proximate to the substrate to receive the emitted radiation and determine the endpoint by determining the intensity of the radiation emitted by the endpointing material.

Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.

Abstract: Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

Abstract: In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly. The present invention also relates to a memory cell array comprising an array of wordlines and digitlines arranged to access respective memory cells within the array. Respective wordlines comprise a poly-metal stack formed over a semiconductor substrate in accordance with the present invention. Additionally, the present invention relates to a computer system comprising a memory cell array of the present invention.

Abstract: An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

Abstract: A method of forming an ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment of the present invention, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

Abstract: A method of forming an ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment of the present invention, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

Abstract: A method of forming an ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment of the present invention, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

Abstract: A method of forming an ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment of the present invention, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

Abstract: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of metal oxide having multiple different metals bonded with oxygen. The layer has varying stoichiometry across its thickness. The layer includes an inner region, a middle region, and an outer region. The middle region has a different stoichiometry than both the inner and outer regions.