Patents by Inventor Viswanathan Nagarajan
Viswanathan Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962318Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.Type: GrantFiled: January 5, 2022Date of Patent: April 16, 2024Assignee: Texas Instruments IncorporatedInventors: Himanshu Varshney, Viswanathan Nagarajan, Charls Babu, Narasimhan Rajagopal, Eeshan Miglani, Visvesvaraya A Pentakota
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Patent number: 11955984Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.Type: GrantFiled: May 31, 2022Date of Patent: April 9, 2024Assignee: Texas Instruments IncorporatedInventors: Viswanathan Nagarajan, Aniket Datta, Nithin Gopinath
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Patent number: 11881867Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Publication number: 20230387932Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Narasimhan RAJAGOPAL, Nithin GOPINATH, Viswanathan NAGARAJAN, Neeraj SHRIVASTAVA, Visvesvaraya A. PENTAKOTA, Harshit MOONDRA, Abhinav CHANDRA
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Publication number: 20230387933Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Viswanathan NAGARAJAN, Aniket DATTA, Nithin GOPINATH
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Publication number: 20220247420Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: ApplicationFiled: September 7, 2021Publication date: August 4, 2022Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Publication number: 20220224349Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.Type: ApplicationFiled: January 5, 2022Publication date: July 14, 2022Inventors: Himanshu Varshney, Viswanathan Nagarajan, Charls Babu, Narasimhan Rajagopal, Eeshan Miglani, Visvesvaraya A. Pentakota
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Patent number: 11309902Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: GrantFiled: December 16, 2019Date of Patent: April 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
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Publication number: 20200119743Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Srinivas Kumar Reddy NARU, Narasimhan RAJAGOPAL, Shagun DUSAD, Viswanathan NAGARAJAN, Visvesvaraya Appala PENTAKOTA
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Patent number: 10581406Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.Type: GrantFiled: June 11, 2018Date of Patent: March 3, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Karthik Khanna S, Chandrasekhar Sriram, Rajendrakumar Joish, Viswanathan Nagarajan
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Patent number: 10541700Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: GrantFiled: January 16, 2019Date of Patent: January 21, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
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Patent number: 10419036Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.Type: GrantFiled: September 10, 2018Date of Patent: September 17, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Viswanathan Nagarajan, Srinivas Kumar Reddy Naru, Narasimhan Rajagopal
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Publication number: 20190280703Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: ApplicationFiled: January 16, 2019Publication date: September 12, 2019Inventors: Srinivas Kumar Reddy NARU, Narasimhan RAJAGOPAL, Shagun DUSAD, Viswanathan NAGARAJAN, Visvesvaraya Appala PENTAKOTA
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Patent number: 10320405Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: GrantFiled: March 1, 2018Date of Patent: June 11, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Publication number: 20190013795Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.Type: ApplicationFiled: June 11, 2018Publication date: January 10, 2019Inventors: Jawaharlal Tangudu, KARTHIK KHANNA S, Chandrasekhar Sriram, Rajendrakumar Joish, Viswanathan Nagarajan
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Publication number: 20190007071Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Viswanathan NAGARAJAN, Srinivas Kumar Reddy NARU, Narasimhan RAJAGOPAL
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Patent number: 10103753Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.Type: GrantFiled: December 8, 2017Date of Patent: October 16, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Viswanathan Nagarajan, Srinivas Kumar Reddy Naru, Narasimhan Rajagopal
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Publication number: 20180191362Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: ApplicationFiled: March 1, 2018Publication date: July 5, 2018Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Patent number: 9941893Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: GrantFiled: April 12, 2017Date of Patent: April 10, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
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Publication number: 20170302287Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.Type: ApplicationFiled: April 12, 2017Publication date: October 19, 2017Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis