Abstract: A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.

Abstract: A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.

Abstract: In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.

Abstract: In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.

Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.

Abstract: A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.

Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.

Abstract: A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.