Patents by Inventor Vivek K. Singh

Vivek K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12129363
    Abstract: The present invention is directed to polyethylene-based compositions suitable for packaging applications, films, and articles. The polyethylene-based composition according to embodiments disclosed herein includes a polyethylene composition having a first polyethylene fraction and a second polyethylene fraction as well as a calcium salt of 1,2-cyclohexanedicarbodylic acid. The polyethylene-based composition can deliver a balance of properties, including barrier properties, for packaging applications.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: October 29, 2024
    Assignee: Dow Global Technologies LLC
    Inventors: Andrew T. Heitsch, Sanjib Biswas, Mridula Kapur, Alexander Williamson, Philip P. Fontaine, Joshua B. Gaubert, Daniel W. Baugh, III, Jin Wang, Didem Oner-Deliormanli, Hitendra K. Singh, Shadid Askar, Arnaldo T. Lorenzo, Mehmet Demirors, Vivek Kalihari
  • Publication number: 20230394647
    Abstract: In order to determine contour edges within a provided image, a plurality of image cells (e.g., groupings of pixels) are created within the image. For each image cell, a numerical value for each of the pixels is compared to a predetermined threshold value to determine comparison values for each pixel. A total numerical value for each image cell may then be determined utilizing the comparison values and numerical values for each pixel within each image cell. An associated contour cell (indicating present contour edges) is then determined for each image cell by comparing the total numerical value for the image cell to a contour cell index. These operations may be performed in parallel by a graphics processing unit (GPU) for each image cell, which may improve a performance of contour edge determination for the image. The stitching of contour edges may also be performed using the GPU, which may provide additional performance improvements for image contour extraction.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Selim Dogru, Kumara Sastry, John Swanson, Vivek K. Singh
  • Patent number: 11663700
    Abstract: A method comprising identifying a set of target features for a plurality of data instances of an input data collection; determining feature values for the set of target features for the plurality of data instances; identifying a plurality of outlier data instances based on the determined feature values; identifying a plurality of noisy data instances from the outlier data instances based on feature values of the plurality of noisy data instances, wherein a noisy data instance is identified based on a determination that noise is present in noisy data instance; and providing an indication of the plurality of noisy data instances.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: John A. Swanson, Vivek K. Singh, Kumara Sastry, Helen F. Parks, I-Tzu Chen
  • Patent number: 11468656
    Abstract: A method comprising identifying a plurality of non-overlapping coarse domains of a region of interest; selecting a subset of the plurality of coarse domains based on a plurality of first diversity metrics determined for the plurality of coarse domains; identifying a plurality of non-overlapping fine domains of the region of interest, wherein each of the fine domains is a portion of one of the coarse domains of the selected subset of the plurality of coarse domains; selecting a subset of the plurality of fine domains based on a plurality of second diversity metrics determined for the plurality of coarse domains; and providing an indication of the selected subset of the plurality of fine domains.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: October 11, 2022
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, Prasad N. Atkar, Vivek K. Singh, Md Ashraful Alam
  • Patent number: 11301982
    Abstract: A method includes identifying a first geometric pattern that failed a design rule check, identifying a second geometric pattern that passed the design rule check, morphing the first geometric pattern based on the second geometric pattern to generate a morphed geometric pattern, wherein the morphed geometric pattern passes the design rule check, and replacing the first geometric pattern with the morphed geometric pattern.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, Hale Erten, Allan Gu, John A. Swanson, Vivek K. Singh, Abde Ali Hunaid Kagalwalla, Mengfei Yang-Flint
  • Patent number: 11282189
    Abstract: Images are accessed representing a status in a fabrication of a semiconductor chip corresponding to a particular stage in the fabrication. Distortion is removed from the images and actual features of the semiconductor chip are extracted from the images. Synthesized ideal features of the semiconductor chip associated with completion of the particular stage in the fabrication are determined from the one or more images. The actual features are compared to the ideal features to determine whether anomalies associated with the particular stage exist in the semiconductor chip.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: John A. Swanson, Kenny K. Toh, Kumara Sastry, Lillian Chang, Manuj Swaroop, Vivek K. Singh
  • Patent number: 11244440
    Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Abde Ali Hunaid Kagalwalla
  • Patent number: 11176658
    Abstract: A method comprising determining a binary classification value for each of a plurality of data instances based on a first threshold value assigned to each of the plurality of data instances; applying at least one clustering model to a first subset of the plurality of data instances to identify one or more dominant clusters of data instances; determining a second threshold value to assign to a second plurality of data instances that are included within the one or more dominant clusters of data instances; and redetermining a binary classification value for each of the plurality of data instances based on the second threshold value assigned to the second plurality of data instances and the first threshold value, wherein the first threshold value is assigned to at least a portion of data instances of the plurality of data instances that are not included in the second plurality of data instances.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Kumara Sastry, Abde Ali Hunaid Kagalwalla
  • Patent number: 11010525
    Abstract: A search engine receives data describing reference geometry and generates a hash based on the reference geometry. A reference bloom filter is generated for the reference geometry based on the hash. The search engine performs a search to determine whether instances of the reference geometry are present in an integrated circuit (IC) layout. The search includes comparing the reference bloom filter with each one of a plurality of bloom filters corresponding to a plurality of subdomains of the IC layout. Based on results of the comparison, one or more subdomains of interest are identified and searched to determine whether the particular reference geometry is present in the subdomain.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, John A. Swanson, Prasad N. Atkar, Vivek K. Singh, Aswin Sreedhar
  • Patent number: 10915691
    Abstract: A semantic pattern extraction system can distill tremendous amounts of silicon wafer manufacturing data to generate a small set of simple sentences (semantic patterns) describing physical design geometries that may explain manufacturing defects. The system can analyze many SEM images for manufacturing defects in areas of interest on a wafer. A tagged continuous itemset is generated from the images, with items comprising physical design feature values corresponding to the areas of interest and tagged with the presence or absence of a manufacturing defect. Entropy-based discretization converts the continuous itemset into a discretized one. Frequent set mining identifies a set of candidate semantic patterns from the discretized itemset. Candidate semantic patterns are reduced using reduction techniques and are scored. A ranked list of final semantic patterns is presented to a user. The final semantic patterns can be used to improve a manufacturing process.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, Vivek K. Singh, Allan Gu, Abde Ali Hunaid Kagalwalla, Saumyadip Mukhopadhyay, Kumara Sastry, Daniel L. Stahlke, Kritika Upreti
  • Patent number: 10885259
    Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, John A. Swanson, Kumara Sastry, Prasad N. Atkar, Vivek K. Singh
  • Patent number: 10877367
    Abstract: A machine readable storage medium, a method and an apparatus. The method comprises selecting a candidate set of parameters from a plurality of available parameters comprising variables that affect an outcome of a lithography process; performing a set of optimizations wherein each optimization of the set of optimizations is subject to a plurality of objectives and tolerances and a set of constraints, wherein performance of said each optimization comprises: modifying values of at least a portion of the candidate set of parameters to derive a predicted outcome for said each optimization; and determining whether a difference between the predicted outcome and an intended outcome is within an error threshold; and if the difference exceeds the error threshold, perform a subsequent optimization, and otherwise generate an input file including modified values, corresponding to a last one of the set of optimizations, for the at least a portion of the candidate set of parameters.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 29, 2020
    Assignee: INTEL CORPORATION
    Inventors: John A. Swanson, Vivek K. Singh, Kumara Sastry, Kshitij Auluck, Saumyadip Mukhopadhyay, Kasyap Thottasserymana Vasudevan
  • Publication number: 20200027021
    Abstract: Reinforcement learning methods are applied to the multi-domain problem of developing photoresist models for advanced semiconductor technologies. In an iterative process, candidate photoresist models are selected or generated, with each model comprising an optical imaging model, one or more analytical chemistry or deformation kernels, and one or more photoresist development model terms. Model parameters to be calibrated in an iteration are selected. The candidate photoresist models are calibrated to best fit photoresist contours extracted from SEM images. Values for the calibration model parameters are determined and the most useful analytical kernels are kept in each model while the others are dropped. A genetic algorithm uses the best calibrated photoresist models from the prior iteration to develop candidate models for the next iteration. The process iterates until no further accuracies can be gained. A residual minimization model can be trained to correct for residual errors in the final model.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Kumara Sastry, Kenny K. Toh, John A. Swanson, Vivek K. Singh, Matthew K. Gumbel, Manuj Swaroop, Selim Dogru
  • Publication number: 20200019052
    Abstract: A machine readable storage medium, a method and an apparatus. The method comprises selecting a candidate set of parameters from a plurality of available parameters comprising variables that affect an outcome of a lithography process; performing a set of optimizations wherein each optimization of the set of optimizations is subject to a plurality of objectives and tolerances and a set of constraints, wherein performance of said each optimization comprises: modifying values of at least a portion of the candidate set of parameters to derive a predicted outcome for said each optimization; and determining whether a difference between the predicted outcome and an intended outcome is within an error threshold; and if the difference exceeds the error threshold, perform a subsequent optimization, and otherwise generate an input file including modified values, corresponding to a last one of the set of optimizations, for the at least a portion of the candidate set of parameters.
    Type: Application
    Filed: August 30, 2019
    Publication date: January 16, 2020
    Inventors: John A. Swanson, Vivek K. Singh, Kumara Sastry, Kshitij Auluck, Saumyadip Mukhopadhyay, Kasyap Thottasserymana Vasudevan
  • Publication number: 20200013161
    Abstract: A method comprising determining a binary classification value for each of a plurality of data instances based on a first threshold value assigned to each of the plurality of data instances; applying at least one clustering model to a first subset of the plurality of data instances to identify one or more dominant clusters of data instances; determining a second threshold value to assign to a second plurality of data instances that are included within the one or more dominant clusters of data instances; and redetermining a binary classification value for each of the plurality of data instances based on the second threshold value assigned to the second plurality of data instances and the first threshold value, wherein the first threshold value is assigned to at least a portion of data instances of the plurality of data instances that are not included in the second plurality of data instances.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Kumara Sastry, Abde Ali Hunaid Kagalwalla
  • Publication number: 20200013157
    Abstract: Images are accessed representing a status in a fabrication of a semiconductor chip corresponding to a particular stage in the fabrication. Distortion is removed from the images and actual features of the semiconductor chip are extracted from the images. Synthesized ideal features of the semiconductor chip associated with completion of the particular stage in the fabrication are determined from the one or more images.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicant: Intel Corporation
    Inventors: John A. Swanson, Kenny K. Toh, Kumara Sastry, Lillian Chang, Manuj Swaroop, Vivek K. Singh
  • Publication number: 20200005451
    Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.
    Type: Application
    Filed: August 30, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Abde Ali Hunaid Kagalwalla
  • Publication number: 20200004921
    Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.
    Type: Application
    Filed: August 30, 2019
    Publication date: January 2, 2020
    Inventors: Bikram Baidya, John A. Swanson, Kumara Sastry, Prasad N. Atkar, Vivek K. Singh
  • Publication number: 20190385300
    Abstract: A method includes identifying a first geometric pattern that failed a design rule check, identifying a second geometric pattern that passed the design rule check, morphing the first geometric pattern based on the second geometric pattern to generate a morphed geometric pattern, wherein the morphed geometric pattern passes the design rule check, and replacing the first geometric pattern with the morphed geometric pattern.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Bikram Baidya, Hale Erten, Allan Gu, John A. Swanson, Vivek K. Singh, Abde Ali Hunaid Kagalwalla, Mengfei Yang-Flint
  • Publication number: 20190325246
    Abstract: A method comprising identifying a plurality of non-overlapping coarse domains of a region of interest; selecting a subset of the plurality of coarse domains based on a plurality of first diversity metrics determined for the plurality of coarse domains; identifying a plurality of non-overlapping fine domains of the region of interest, wherein each of the fine domains is a portion of one of the coarse domains of the selected subset of the plurality of coarse domains; selecting a subset of the plurality of fine domains based on a plurality of second diversity metrics determined for the plurality of coarse domains; and providing an indication of the selected subset of the plurality of fine domains.
    Type: Application
    Filed: June 29, 2019
    Publication date: October 24, 2019
    Inventors: Bikram Baidya, Prasad N. Atkar, Vivek K. Singh, Md Ashraful Alam