Patents by Inventor Vivek K. Singh

Vivek K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
    Patent number: 6898781
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
    Publication number: 20040025140
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Application
    Filed: July 30, 2003
    Publication date: February 5, 2004
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
    Patent number: 6625802
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
    Publication number: 20030149956
    Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 7, 2003
    Inventors: Vivek K. Singh, John Ernst Bjorkholm, Francisco A. Leon
  • Photo-lithographic method to print a line-space pattern with a pitch equal to half the pitch of the mask
    Patent number: 6373553
    Abstract: An optical lithography system and method which utilizes a mask pattern and forms Talbot sub-images of an illuminated grating onto a photosensitive target to print an image pattern on the photosensitive target such that the image pattern printed has a pitch equal to half the pitch of the mask pattern.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: April 16, 2002
    Assignee: Intel Corp.
    Inventor: Vivek K. Singh