Patents by Inventor Vivek Mohan

Vivek Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12471901
    Abstract: The present invention provides an instrument assembly that is expandable in steps for providing precise measurement of bone gap and distraction of bone in a controlled manner. It discloses a tool performing expandable Bi-Surface Mechanism to expand a bi-compartmental structure. The disclosed system is equipped with two active surfaces (Bottom base and a top plate) between which a force is applied to move the surfaces in relation to each other for providing precise measurement of bone gap and distraction of bone in a controlled manner. Additionally, the control mechanism of the present invention includes applying direct and/or measured/graduated separation force between the two surfaces and able to deliver haptic and sensor-based feedback to the surgeon for the critical ligament tensioning and balancing aspects of the procedure.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 18, 2025
    Inventors: Vivek Mohan, Robert S. Namba
  • Publication number: 20250342135
    Abstract: Methods and apparatuses for on-die logic that allow dies, such as a system-on-a-chips (SoCs), to support multiple memory devices in various die configurations. In one example, a die package comprises a first memory device and a system-on-a-chip (SoC). The SoC includes a first plurality of physical layer interfaces electrically connected to the first memory device, wherein the SoC and the first memory device are in a first die package configuration. The SoC also includes a second plurality of physical layer interfaces configured to electrically connect to a second memory device, wherein the SoC and the second memory device are in a second die package configuration In some instances, the first die package configuration is package-on-package (POP), and the second die configuration is system-in-a-package (SiP).
    Type: Application
    Filed: May 1, 2024
    Publication date: November 6, 2025
    Inventors: Vivek MOHAN, Boris Dimitrov ANDREEV, Vaishnav SRINIVAS, Piyush GUPTA
  • Publication number: 20250294888
    Abstract: A die includes a first set of physical layer (PHY) blocks arranged in a first column, wherein the first column extends along a side of the die. The die also includes a second set of PHY blocks arranged in a second column adjacent to the first column. The first set of PHY blocks include a first PHY block, the second set of PHY blocks include a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.
    Type: Application
    Filed: March 18, 2024
    Publication date: September 18, 2025
    Inventors: Srivatsan THIRUVENGADAM, Vivek MOHAN
  • Patent number: 12367324
    Abstract: A method of manufacturing a structural part includes accessing memory storing code for a software tool to determine a template profile for the structural part. The method includes executing the code to cause an apparatus to execute the software tool for accessing a 3D model of the structural part. The method also includes generating a profile from the 3D model and dimensioning the profile, and accessing and searching a database for stock profiles that match search criteria that include the dimension measurements of the profile set as lower bounds of the corresponding dimension measurements. The method also includes performing a decision analysis to evaluate attributes of the matching stock profiles and identify a selected stock profile. The method also includes outputting an indication of the selected stock profile for manufacturing the structural part from a stock structural part having a cross-sectional profile corresponding to the selected stock profile.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: July 22, 2025
    Assignee: The Boeing Company
    Inventors: Eric S Lester, Jr., Vivek Mohan, Venkata Narasimha Ravi Udali, Shobhit Rastogi, John Gilotti, John Henry Moselage, III
  • Publication number: 20240245873
    Abstract: A system, method and device for integrating the application of acoustic resonance, as correlated with a wearer of the device, with the application of a continuous positive airway pressure system. The aspects disclosed herein are directed to improving CPAP compliance and efficacy. In various embodiments, the acoustic resonance may be applied directly to a wearer's paranasal sinus, or to an air passageway that communicates with an orifice of a person.
    Type: Application
    Filed: January 24, 2023
    Publication date: July 25, 2024
    Inventors: Elan Hekier, Bryant Lin, Paramesh Gopi, Vivek Mohan, Peter H. Hwang
  • Publication number: 20220284148
    Abstract: A method of managing a design lifecycle of a structural part includes accessing memory storing computer-readable program code for identifying a supplier for the structural part. The method includes executing the code to cause an apparatus to identify the supplier. The method also includes generating a first design of the structural part, the first design describing a geometry of the structural part and requirements for attributes of the structural part. The method also includes performing a search of a database of existing designs for a second design based on search criteria including multiple ones of the geometry and the requirements, and selecting a design from the first design and the second design based on the search. The method also includes performing a multiple-criteria decision analysis to evaluate the design, identifying the supplier from multiple suppliers, and outputting an indication of the supplier for use in ordering of the structural part.
    Type: Application
    Filed: February 4, 2022
    Publication date: September 8, 2022
    Inventors: Eric S. Lester, Samir Abad, George Bojko, Abul Azad, Venkata Narasimha Ravi Udali, Vivek Mohan
  • Publication number: 20220067223
    Abstract: A method of manufacturing a structural part includes accessing memory storing code for a software tool to determine a template profile for the structural part. The method includes executing the code to cause an apparatus to execute the software tool for accessing a 3D model of the structural part. The method also includes generating a profile from the 3D model and dimensioning the profile, and accessing and searching a database for stock profiles that match search criteria that include the dimension measurements of the profile set as lower bounds of the corresponding dimension measurements. The method also includes performing a decision analysis to evaluate attributes of the matching stock profiles and identify a selected stock profile. The method also includes outputting an indication of the selected stock profile for manufacturing the structural part from a stock structural part having a cross-sectional profile corresponding to the selected stock profile.
    Type: Application
    Filed: July 15, 2021
    Publication date: March 3, 2022
    Inventors: Eric S Lester, JR., Vivek Mohan, Venkata Narasimha Ravi Udali, Shobhit Rastogi, John Gilotti, John Henry Moselage, III
  • Publication number: 20210378651
    Abstract: The present invention provides an instrument assembly that is expandable in steps for providing precise measurement of bone gap and distraction of bone in a controlled manner. It discloses a tool performing expandable Bi-Surface Mechanism to expand a bi-compartmental structure. The disclosed system is equipped with two active surfaces (Bottom base and a top plate) between which a force is applied to move the surfaces in relation to each other for providing precise measurement of bone gap and distraction of bone in a controlled manner. Additionally, the control mechanism of the present invention includes applying direct and/or measured/graduated separation force between the two surfaces and able to deliver haptic and sensor-based feedback to the surgeon for the critical ligament tensioning and balancing aspects of the procedure.
    Type: Application
    Filed: April 11, 2019
    Publication date: December 9, 2021
    Inventors: Vivek Mohan, Robert S. Namba
  • Patent number: 8605604
    Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise: a wireless local-area network (WLAN) module comprising a receiver configured to receive a WLAN signal into the WLAN module; a transmitter; and a loopback controller configured to selectively loop back the WLAN signal to the transmitter, wherein the transmitter is configured to transmit the looped-back WLAN signal from the WLAN module.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 10, 2013
    Assignee: Marvell International Ltd.
    Inventors: Vivek Mohan, Hsui-Ping Peng
  • Patent number: 8593203
    Abstract: An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: November 26, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Vijay Shankar, Abheek Gupta, Vaishnav Srinivas, Vivek Mohan
  • Patent number: 8184414
    Abstract: A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: May 22, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Reza Jalilizeinali, Sreeker Dundigal, Vivek Mohan, Thomas R. Toms
  • Patent number: 8138814
    Abstract: A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: March 20, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Vijay Shankar, Abheek Gupta, Vaishnav Srinivas, Vivek Mohan
  • Patent number: 8106699
    Abstract: A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: January 31, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Vijay Shankar, Abheek Gupta, Vaishnav Srinivas, Vivek Mohan
  • Patent number: 8063674
    Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: November 22, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Chang Ki Kwon, Vivek Mohan
  • Patent number: 8040645
    Abstract: A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: October 18, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Reza Jalilizeinali, Sreeker Dundigal, Vivek Mohan
  • Patent number: 7843234
    Abstract: A break-before-make predriver for disabling a PFET of an output driver before enabling an NFET, and vice versa. The predriver includes an input inverter, two cross-coupled inverters, and output buffers. The predriver provides enhanced break-before-make action through sizing the NFETs larger than the PFETs in the predriver's cross-coupled inverters. The input inverter, the cross-coupled inverters and the first and second output buffers are sized with respect to each other such that substantially equal break before make action is provided on both rising and falling edges. The predriver also includes level-shifting capabilities through a different voltage supply at the PFETs of the cross-coupled inverter. The predriver also includes two data output nodes for connection to the two inputs of an output driver. The predriver provides for tristate action by disabling the signal from the predriver output nodes.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: November 30, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Vivek Mohan
  • Patent number: 7804334
    Abstract: A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: September 28, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Vijay Shankar, Abheek Gupta, Vaishnav Srinivas, Vivek Mohan
  • Patent number: 7772887
    Abstract: A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: August 10, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Vijay Shankar, Abheek Gupta, Vaishnav Srinivas, Vivek Mohan
  • Patent number: 7772831
    Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: August 10, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Tauseef Kazi, Jeff Gemar, Vaishnav Srinivas, Vivek Mohan
  • Publication number: 20100194200
    Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 5, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chang Ki Kwon, Vivek Mohan