Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution include a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each signal line that isolates the signal line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state. This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary lines.

Abstract: The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an input terminal of one of the access transistors so that the access transistors coupled to the outputs from one of the memory cells share one of the wordlines and are coupled to different bitlines. A wordline driver is coupled to each wordline with the ability of generating a variable voltage at its output responsive to the wordline driver control inputs and voltage at its ground supply node. A plurality of grouped voltage supply lines are coupled to a group of the wordline drivers for inducing a variable reference voltage or ground supply at the ground supply node. A voltage switching logic switches the voltage for the variable ground supply responsive to a ground control input.

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

Abstract: A logic device operates with reduced leakage current. Controllability is achieved by using a reference voltage to control the amount of leakage reduction. A method of temperature dependent reference voltage generation is given which maintains virtual supply in acceptable range to provide sufficient noise margin in logic devices including memory cells.

Abstract: A sense amplifier includes a feedback controlled bit line access scheme that feeds a sense amplifier output signal back to control operation of its associated bit line access transistor. This feedback may be implemented using a pair of inverter circuits each coupling a respective output signal to the control gate of the associated access transistor. Alternatively, the feedback may be implement using a logic gate which logically combines the sense amplifier output signals together to generate an output signal for controlling operation of both access transistors. The logic gate is preferably a NAND gate. The sense amplifier further includes a cross-connected feedback inversion circuit which inverts a sense amplifier output signal from a first latch inverter for application to a conducting line of a second latch inverter.

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state.

Abstract: A sense amplifier includes a feedback controlled bit line access scheme that feeds a sense amplifier output signal back to control operation of its associated bit line access transistor. This feedback may be implemented using a pair of inverter circuits each coupling a respective output signal to the control gate of the associated access transistor. Alternatively, the feedback may be implement using a logic gate which logically combines the sense amplifier output signals together to generate an output signal for controlling operation of both access transistors. The logic gate is preferably a NAND gate. The sense amplifier further includes a cross-connected feedback inversion circuit which inverts a sense amplifier output signal from a first latch inverter for application to a conducting line of a second latch inverter.

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.