Patents by Inventor Vivek Singhal
Vivek Singhal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170194949Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventors: Sudesh Chandra Srivastava, Vivek Singhal
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Patent number: 9535123Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.Type: GrantFiled: December 31, 2015Date of Patent: January 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajesh Kumar Mittal, Wilson Pradeep, Vivek Singhal
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Publication number: 20160356849Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Inventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
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Patent number: 9448284Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: GrantFiled: May 8, 2014Date of Patent: September 20, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
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Publication number: 20160266202Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.Type: ApplicationFiled: December 31, 2015Publication date: September 15, 2016Inventors: Rajesh Kumar Mittal, Wilson Pradeep, Vivek Singhal
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Patent number: 9419630Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.Type: GrantFiled: December 29, 2014Date of Patent: August 16, 2016Assignee: Texas Instruments IncorporatedInventors: Sreenath Narayanan Potty, Vivek Singhal, Sumanth Reddy Poddutur
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Publication number: 20160191066Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.Type: ApplicationFiled: December 29, 2014Publication date: June 30, 2016Inventors: Sreenath Narayanan Potty, Vivek Singhal, Sumanth Reddy Poddutur
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Patent number: 9319045Abstract: A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip includes a first transistor having a drain electrode coupled to a first terminal of a power switch having a second terminal coupled to a first reference voltage, the first transistor having a gate electrode, a body electrode, and a source electrode. The source electrode and body electrodes are coupled to a second reference voltage. The first transistor has a relatively high first gate leakage current that flows from its gate electrode to its body electrode if the power switch is open and a voltage of the gate electrode of the first transistor representing a first logic level exceeds a voltage of the body electrode by more than a first predetermined amount.Type: GrantFiled: December 29, 2014Date of Patent: April 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudesh Chandra Srivastava, Vivek Singhal
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Publication number: 20150323596Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicant: Texas Instruments IncorporatedInventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
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Patent number: 9053273Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.Type: GrantFiled: July 20, 2012Date of Patent: June 9, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sumanth Reddy Poddutur, Prakash Narayanan, Vivek Singhal
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Patent number: 8981821Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.Type: GrantFiled: January 11, 2013Date of Patent: March 17, 2015Assignee: Texas Instruments IncorporatedInventors: Sreenath Narayanan Potty, Jasbir Singh Nayyar, Vivek Singhal
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Publication number: 20140197875Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.Type: ApplicationFiled: January 11, 2013Publication date: July 17, 2014Applicant: Texas Instruments IncorporatedInventors: Sreenath Narayanan Potty, Jasbir Singh Nayyar, Vivek Singhal
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Patent number: 8750805Abstract: A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.Type: GrantFiled: December 16, 2010Date of Patent: June 10, 2014Assignee: Texas Instruments IncorporatedInventors: Vivek Singhal, Senthilkannan Chandrasekaran, Sumanth Poddutur, Jasbir Singh
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Patent number: 8698539Abstract: A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.Type: GrantFiled: January 11, 2013Date of Patent: April 15, 2014Assignee: Texas Instruments IncorporatedInventors: Jasbir Singh Nayyar, Sreenath Narayanan Potty, Mukesh Kumar, Vivek Singhal
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Publication number: 20140021993Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: Texas Instruments IncorporatedInventors: SUMANTH REDDY PODDUTUR, Prakash Narayanan, Vivek Singhal
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Publication number: 20120154010Abstract: A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.Type: ApplicationFiled: December 16, 2010Publication date: June 21, 2012Applicant: Texas Instruments IncorporatedInventors: Vivek Singhal, Senthilkannan Chandrasekaran, Sumanth Poddutur, Jasbir Singh
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Patent number: 8185534Abstract: A plurality of source records are obtained from a plurality of source record databases, where the plurality of source records includes information regarding a common entity. A consolidated record is generated including selected information regarding the common entity, obtained from the plurality of source records. Identifier prefix values, different for each of the plurality of source record databases, are obtained and a plurality of source record identifiers are obtained that are stored in the source record databases and are associated with the plurality of source records. An ordered set of candidate consolidation identifiers is determined based on prepending identifier prefix values to the source record identifiers. A consolidated record identifier is determined based on selecting an extreme value of the set of candidate consolidation identifiers, and is stored in association with the consolidated record in a consolidated record database for identification and retrieval of the consolidated record.Type: GrantFiled: February 5, 2009Date of Patent: May 22, 2012Assignee: Google Inc.Inventors: Vivek Singhal, Zilin Du, Deepak Kher, Akhil Vidwans
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Publication number: 20120062298Abstract: A circuit for mitigating hold closure. The circuit includes a flip-flop having a clock input and an output. The circuit also includes a multiplexer. The multiplexer includes a select input coupled to the clock input of the flip-flop. The multiplexer also includes a first data input coupled to the output of the flip-flop. Further, the multiplexer includes an output coupled to a second data input of the multiplexer.Type: ApplicationFiled: September 15, 2010Publication date: March 15, 2012Applicant: Texas Instruments IncorporatedInventors: Sumanth Reddy PODDUTUR, Prakash Narayanan, Vivek Singhal
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Patent number: 8058902Abstract: A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first flip flop and a second flip flop, coupled to the CGC, are responsive to first type of edge of the clock signal to output the first signal and the second signal. A finite state machine (FSM), coupled to the CGC, the first flip flop and the second flip flop, is responsive to second type of edge of the clock signal to detect early arrival of one of the first signal and the second signal with respect to each other, and to generate first control signal and second control signal. A first programmable delay element and a second programmable delay element, coupled to the FSM, delays first input signal based on the first control signal and second input signal based on the second control signal.Type: GrantFiled: June 11, 2010Date of Patent: November 15, 2011Assignee: Texas Instruments IncorporatedInventors: Sahil Khurana, Vivek Singhal, Yogesh Darwhekar
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Publication number: 20080034251Abstract: Application-level replication, the synchronization of data updates within a cluster of application servers, may be provided by having application servers themselves synchronize all updates to multiple redundant databases, precluding the need for database-level replication. This may be accomplished by first sending a set of database modifications requested by the transaction to a first database. Then a message may be placed in one or more message queues, the message indicating the objects inserted, updated, or deleted in the transaction. Then a commit command may be sent to the first database. The set of database modifications and a commit command may then be sent to second database. This allows for transparent synchronization of the database and quick recovery from a database failure, while imposing little performance or network overhead.Type: ApplicationFiled: October 17, 2007Publication date: February 7, 2008Applicant: Progress Software CorporationInventors: Vivek Singhal, Ian Emmons