Abstract: An apparatus is disclosed for transmission setting selection. In an example aspect, an apparatus includes a wireless interface device with a communication processor and a radio-frequency front-end. The communication processor is configured to provide a signal. The radio-frequency front-end is coupled to the communication processor and configured to accept the signal. The radio-frequency front-end includes an amplifier configured to amplify the signal based on one or more amplifier settings. The wireless interface device is configured to adjust the one or more amplifier settings responsive to an output power being changed with a gain being unchanged.

Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Abstract: An antenna system includes: a ground conductor; a substrate; a pair of planar dipole conductors disposed such that at least a portion of the substrate is disposed between the ground conductor and the pair of dipole conductors; a pair of energy couplers each electrically connected to a respective one of the pair of dipole conductors; and a pair of isolated lobes including electrically-conductive material. The pair of isolated lobes are electrically separate from the pair of dipole conductors and the pair of energy couplers, and disposed between the pair of dipole conductors and the ground conductor.

Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Abstract: Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

Abstract: An antenna system includes: a ground conductor; a substrate; a pair of planar dipole conductors disposed such that at least a portion of the substrate is disposed between the ground conductor and the pair of dipole conductors; a pair of energy couplers each electrically connected to a respective one of the pair of dipole conductors; and a pair of isolated lobes including electrically-conductive material. The pair of isolated lobes are electrically separate from the pair of dipole conductors and the pair of energy couplers, and disposed between the pair of dipole conductors and the ground conductor.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

Abstract: Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related DNA sensing device may be formed by a process comprising forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for sensing. One example apparatus for sensing includes a sensor configured to supply a current indicative of a parameter and a bipolar transistor having a base coupled to the sensor to receive the current, the bipolar transistor being configured to generate an amplified current based on the current. The apparatus may also include a measurement circuit coupled to the bipolar transistor and configured receive the amplified current.

Abstract: Certain aspects of the present disclosure provide systems and methods for performing a power amplifier characterization. One example method generally includes determining, by a user equipment, if a condition associated with a power amplifier characterization is met. In certain aspects, the method includes determining, by the user equipment, a calibration gap after the condition is met. The method also includes performing, by the user equipment, the power amplifier characterization of the one or more power amplifiers of the user equipment during the calibration gap.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related DNA sensing device may be formed by a process comprising forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.

Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related method may include forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.

Abstract: An ionic current sensor array includes a master bias generator and a plurality of sensing cells. The master bias generator is configured to generate a bias voltage. Each sensing cell includes an ionic current sensor, an integrating capacitor, a sense transistor coupled between the integrating capacitor and the ionic current sensor, and an amplifier coupled to provide a reference voltage to bias the ionic current sensor. The amplifier includes a first transistor and a second transistor. The first transistor is coupled to receive the bias voltage, and the second transistor is coupled to the first transistor to provide the reference voltage to the ionic current sensor. The second transistor is also coupled between a source of the sense transistor and the gate of the sense transistor.

Abstract: A pair of stacked ground coplanar waveguides (GCPWs) is provided in two consecutive metal layers that are deposited on opposing surfaces of a dielectric layer. A first metal layer on a first side of the dielectric layer forms a first signal trace and an upper ground plane for a first GCPW in the pair. Similarly, a second metal layer on a second surface of the dielectric layer forms a second signal trace and an upper ground plane for a second GCPW in the pair.