Abstract: Techniques for improving the DNA sensing signal of nanopore-based DNA sensing devices are disclosed. A related DNA sensing device may include a first electrode, a second electrode, a hydrophobic layer having a nanopore disposed therein, and a negative capacitance layer.

Abstract: An ionic current sensor array includes a master bias generator and a plurality of sensing cells. The master bias generator is configured to generate a bias voltage. Each sensing cell includes an ionic current sensor, an integrating capacitor, a sense transistor coupled between the integrating capacitor and the ionic current sensor, and an amplifier coupled to provide a reference voltage to bias the ionic current sensor. The amplifier includes a first transistor and a second transistor. The first transistor is coupled to receive the bias voltage, and the second transistor is coupled to the first transistor to provide the reference voltage to the ionic current sensor. The second transistor is also coupled between a source of the sense transistor and the gate of the sense transistor.

Abstract: Techniques for increasing the lifespan of a nanopore DNA sensing device are disclosed. A related method may include forming a first electrode, forming a second electrode, disposing the first electrode and second electrode within an insulator, and disposing a lipid bilayer having a nanopore between the first electrode and second electrode. The forming of the second electrode may comprise forming a silver (Ag) layer, pressing a mold into the Ag layer to form a pattern in the Ag layer, removing the mold from the Ag layer, and exposing the Ag layer to an electrolyte.

Abstract: A pair of stacked ground coplanar waveguides (GCPWs) is provided in two consecutive metal layers that are deposited on opposing surfaces of a dielectric layer. A first metal layer on a first side of the dielectric layer forms a first signal trace and an upper ground plane for a first GCPW in the pair. Similarly, a second metal layer on a second surface of the dielectric layer forms a second signal trace and an upper ground plane for a second GCPW in the pair.

Abstract: Techniques for simultaneously receiving multiple transmitted signals with independent gain control are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a low noise amplifier (LNA) and first and second receive circuits. The LNA amplifies a receiver input signal and provides (i) a first amplified signal for a first set of at least one transmitted signal being received and (ii) a second amplified signal for a second set of at least one transmitted signal being received. The first receive circuit scales the first amplified signal based on a first adjustable gain selected for the first set of transmitted signal(s). The second receive circuit scales the second amplified signal based on a second adjustable gain selected for the second set of transmitted signal(s). The first and second adjustable gains may be independently selected, e.g., based on the received powers of the transmitted signals.

Abstract: High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for sensing. One example apparatus for sensing includes a sensor configured to supply a current indicative of a parameter and a bipolar transistor having a base coupled to the sensor to receive the current, the bipolar transistor being configured to generate an amplified current based on the current. The apparatus may also include a measurement circuit coupled to the bipolar transistor and configured receive the amplified current.

Abstract: Various aspects of the present disclosure provide an apparatus for wireless communication. The apparatus may include an integrated circuit, an antenna, and a module located adjacent to the antenna. The module may include at least one of a power amplifier or a low-noise amplifier. The power amplifier may be configured to amplify a signal received from the integrated circuit for transmission by the antenna. The low-noise amplifier may be configured to amplify a signal received from the antenna for reception by the integrated circuit. The module may be separate from the integrated circuit. A length of a feed line connecting the antenna and the module may be less than a length of a feed line connecting the module and the integrated circuit. The module may also include a switching mechanism configured to switch operation of the module between transmission and reception.

Abstract: Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

Abstract: The systems and method described herein provide efficient wireless communication in a millimeter wave (MMW) phased array system. The system may comprise a plurality of antenna elements, each of the plurality of antenna elements coupled to a transceiver and transceiver having at least one power amplifier. The system may further comprise a gain controller configured to enable or disable the transceivers in response to a power detector output indicating that one or more antenna elements are blocked. Disabling certain transceivers of blocked antenna elements enables the power amplifiers associated with the unblocked antenna elements to continue to operate at maximum efficiency.

Abstract: A method, an apparatus, and system for filtering a signal in a carrier aggregation system are provided. The apparatus processes carriers via at least two respective paths. Each path receives, via a transconducting module, an input signal and generates a current signal based on the input signal, shifts, via a mixing module, a frequency of the current signal by mixing the current signal with a local oscillating signal corresponding to a respective path, and generates, via an amplifying module, an output voltage signal based on the frequency-shifted signal and a response of the respective path. The apparatus attenuates, via a filtering module, a jamming signal in the input signal to produce responses for the at least two paths, respectively. A response for the respective path has a maximum input impedance at a frequency of the local oscillating signal corresponding to the respective path.

Abstract: Front-end radio frequency (RF) filters with embedded impedance transformation are disclosed. In an exemplary design, an apparatus includes an active circuit and an RF filter. The active circuit receives an input signal and provides an output signal. The RF filter is operatively coupled to an antenna and the active circuit and performs filtering for the input signal or output signal. The RF filter is impedance matched to the active circuit and includes a non-LC filter. In an exemplary design, the active circuit includes a low noise amplifier (LNA), and the RF filter includes a receive (RX) filter having an output impedance that is matched to an input impedance of the LNA. In another exemplary design, the active circuit includes a power amplifier, and the RF filter includes a transmit (TX) filter having an input impedance that is matched to an output impedance of the power amplifier.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for spiking neural computation of general linear systems. One example aspect is a neuron model that codes information in the relative timing between spikes. However, synaptic weights are unnecessary. In other words, a connection may either exist (significant synapse) or not (insignificant or non-existent synapse). Certain aspects of the present disclosure use binary-valued inputs and outputs and do not require post-synaptic filtering. However, certain aspects may involve modeling of connection delays (e.g., dendritic delays). A single neuron model may be used to compute any general linear transformation x=AX+BU to any arbitrary precision. This neuron model may also be capable of learning, such as learning input delays (e.g., corresponding to scaling values) to achieve a target output delay (or output value). Learning may also be used to determine a logical relation of causal inputs.

Abstract: Techniques for providing a jammer-resistant noise-cancelling receiver front end with band-pass impedance matching and good power efficiency. In an aspect, the center frequency of the band-pass impedance matching advantageously tracks the local oscillator frequency. In an aspect, first and second receive signal paths are provided, with an R-C network coupled to the output of the second receive signal path. The resistance of the R-C network may be selected to provide band-pass impedance matching to the RF input signal. The current outputs of the first and second signal paths are combined using a trans-impedance amplifier (TIA). In an aspect, the TIA may be implemented using a dual input transconductor amplifier to further optimize the noise performance and power efficiency features of the disclosure.

Abstract: A wireless device is described. The wireless device includes an antenna. The wireless device also includes a hybrid transformer. The wireless device further includes a frequency matching termination port. The frequency matching termination port provides impedance matching with the antenna at multiple frequencies. The frequency matching termination port may include multiple resistors, inductors and capacitors that can be switched in/out.

Abstract: Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.

Abstract: A method for configuring an artificial neuron includes receiving a set of input spike trains comprising asynchronous pulse modulation coding representations. The method also includes generating output spikes representing a similarity between the set of input spike trains and a spatial-temporal filter.

Abstract: Exemplary embodiments are directed to systems, devices, and methods for mitigating effects of transmit signal leakage. A transceiver may include a transmitter and a receiver. The transceiver may further include a multi-tap analog adaptive filter coupled to each of the transmitter and the receiver and configured to generate an estimated transmit leakage signal based on at least a portion of a transmit signal from the transmitter and an error signal from the receiver.

Abstract: Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

Abstract: Certain aspects of the present disclosure support a local competitive learning rule applied in a computational network that leads to sparse connectivity among processing units of the network. The present disclosure provides a modification to the Oja learning rule, modifying the constraint on the sum of squared weights in the Oja rule. This constraining can be intrinsic and local as opposed to the commonly used multiplicative and subtractive normalizations, which are explicit and require the knowledge of all input weights of a processing unit to update each one of them individually. The presented rule provides convergence to a weight vector that is sparser (i.e., has more zero elements) than the weight vector learned by the original Oja rule. Such sparse connectivity can lead to a higher selectivity of processing units to specific features, and it may require less memory to store the network configuration and less energy to operate it.