Patents by Inventor Vladimir Mikhalev
Vladimir Mikhalev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973031Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.Type: GrantFiled: December 16, 2022Date of Patent: April 30, 2024Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Haitao Liu, Vladimir Mikhalev
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Patent number: 11935883Abstract: Capacitor structures, and apparatus containing similar capacitor structures, might include a first conductive region having a first portion and second and third portions extending from an upper surface of its first portion, a second conductive region having a first portion and a second portion extending from an upper surface of its first portion, a dielectric overlying the second portion of the first conductive region, a conductor overlying the dielectric, and a conductive element overlying the third portion of the first conductive region and overlying the second portion of the second conductive region, wherein the first conductive region has a first conductivity type and the second conductive region has a second conductivity type different than the first conductivity type.Type: GrantFiled: January 12, 2023Date of Patent: March 19, 2024Assignee: Lodestar Licensing Group LLCInventors: Vladimir Mikhalev, Michael Violette
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Patent number: 11848053Abstract: Transistors, and memories including such transistors, might include an active area having a first conductivity type, first and second source/drain regions in the active area and having a second conductivity type, and a plurality of control gates between the first and second source/drain regions and the second source/drain region, wherein each control gate of the plurality of control gates includes a respective first control gate portion overlying a first side of the active area, and a respective second control gate portion connected to its respective first control gate portion that is either adjacent to a second side of the active area orthogonal to the first side of the active area, or underlying a second side of the active area opposite the first side of the active area.Type: GrantFiled: January 10, 2023Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Haitao Liu
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Patent number: 11790995Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.Type: GrantFiled: August 12, 2021Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Vladimir Mikhalev
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Patent number: 11756792Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.Type: GrantFiled: June 12, 2020Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Michael Violette, Vladimir Mikhalev
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Publication number: 20230170344Abstract: Capacitor structures, and apparatus containing similar capacitor structures, might include a first conductive region having a first portion and second and third portions extending from an upper surface of its first portion, a second conductive region having a first portion and a second portion extending from an upper surface of its first portion, a dielectric overlying the second portion of the first conductive region, a conductor overlying the dielectric, and a conductive element overlying the third portion of the first conductive region and overlying the second portion of the second conductive region, wherein the first conductive region has a first conductivity type and the second conductive region has a second conductivity type different than the first conductivity type.Type: ApplicationFiled: January 12, 2023Publication date: June 1, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Vladimir Mikhalev, Michael Violette
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Publication number: 20230123487Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Inventors: Michael A. Smith, Haitao Liu, Vladimir Mikhalev
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Publication number: 20230046480Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Michael A. Smith, Vladimir Mikhalev
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Patent number: 11568934Abstract: Multi-gate transistors, as well as apparatus containing such multi-gate transistors and methods of forming such multi-gate transistors, might facilitate gating voltages in integrated circuit devices. Such multi-gate transistors might include an active area having a first conductivity type, a first source/drain region in the active area and having a second conductivity type different than the first conductivity type, a second source/drain region in the active area and having the second conductivity type, and a plurality of control gates adjacent the active area between the first source/drain region and the second source/drain region, wherein each control gate of the plurality of control gates comprises a respective plurality of control gate portions, and wherein, for a particular control gate of the plurality of control gates, each control gate portion of its respective plurality of control gate portions is adjacent the active area in a respective plane of a plurality of different planes.Type: GrantFiled: April 6, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Haitao Liu
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Patent number: 11569221Abstract: Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.Type: GrantFiled: June 25, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Violette
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Publication number: 20230017305Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.Type: ApplicationFiled: April 27, 2022Publication date: January 19, 2023Inventors: Mattia Cichocki, Vladimir Mikhalev, Phani Bharadwaj Vanguri, James Eric Davis, Kenneth William Marr, Chiara Cerafogli, Michael James Irwin, Domenico Tuzi, Umberto Siciliani, Alessandro Alilla, Andrea Giovanni Xotta, Chung-Ping Wu, Luigi Marchese, Pasquale Conenna, Joonwoo Nam, Ishani Bhatt, Fulvio Rori, Andrea D'Alessandro, Michele Piccardi, Aleksey Prozapas, Luigi Pilolli, Violante Moschiano
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Patent number: 11557537Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.Type: GrantFiled: August 6, 2020Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Haitao Liu, Vladimir Mikhalev
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Publication number: 20220319599Abstract: Multi-gate transistors, as well as apparatus containing such multi-gate transistors and methods of forming such multi-gate transistors, might facilitate gating voltages in integrated circuit devices. Such multi-gate transistors might include an active area having a first conductivity type, a first source/drain region in the active area and having a second conductivity type different than the first conductivity type, a second source/drain region in the active area and having the second conductivity type, and a plurality of control gates adjacent the active area between the first source/drain region and the second source/drain region, wherein each control gate of the plurality of control gates comprises a respective plurality of control gate portions, and wherein, for a particular control gate of the plurality of control gates, each control gate portion of its respective plurality of control gate portions is adjacent the active area in a respective plane of a plurality of different planes.Type: ApplicationFiled: April 6, 2021Publication date: October 6, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Vladimir Mikhalev, Haitao Liu
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Publication number: 20220181341Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Haitao Liu, Michael Violette, Mark A. Helm, Guangyu Huang, Vladimir Mikhalev
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Publication number: 20220044994Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.Type: ApplicationFiled: August 6, 2020Publication date: February 10, 2022Inventors: Michael A. Smith, Haitao Liu, Vladimir Mikhalev
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Publication number: 20210320099Abstract: Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Vladimir Mikhalev, Michael Violette
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Patent number: 11063034Abstract: Capacitor structures including a first island of a first conductive region and a second island of the first conductive region having a first conductivity type, an island of a second conductive region having a second conductivity type different than the first conductivity type, a dielectric overlying the first island of the first conductive region, a conductor overlying the dielectric, and a terminal of a diode overlying the second island of the first conductive region and overlying the island of the second conductive region.Type: GrantFiled: June 27, 2019Date of Patent: July 13, 2021Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Violette
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Publication number: 20200411634Abstract: Capacitor structures including a first island of a first conductive region and a second island of the first conductive region having a first conductivity type, an island of a second conductive region having a second conductivity type different than the first conductivity type, a dielectric overlying the first island of the first conductive region, a conductor overlying the dielectric, and a terminal of a diode overlying the second island of the first conductive region and overlying the island of the second conductive region.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Vladimir Mikhalev, Michael Violette
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Publication number: 20200303192Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.Type: ApplicationFiled: June 12, 2020Publication date: September 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael Violette, Vladimir Mikhalev
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Patent number: 10727062Abstract: Methods of forming a portion of an integrated circuit include forming a patterned mask having an opening and exposing a surface of a semiconductor material, forming a first doped region at a first level of the semiconductor material through the opening, and isotropically removing a portion of the patterned mask to increase a width of the opening. The methods further include forming a second doped region at a second level of the semiconductor region through the opening after isotropically removing the portion of the patterned mask, wherein the second level is closer to the surface of the semiconductor material than the first level.Type: GrantFiled: February 9, 2018Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Michael Violette, Vladimir Mikhalev