Patents by Inventor Vladimir Mikhalev
Vladimir Mikhalev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190206688Abstract: Methods of forming a portion of an integrated circuit include forming a patterned mask having an opening and exposing a surface of a semiconductor material, forming a first doped region at a first level of the semiconductor material through the opening, and isotropically removing a portion of the patterned mask to increase a width of the opening. The methods further include forming a second doped region at a second level of the semiconductor region through the opening after isotropically removing the portion of the patterned mask, wherein the second level is closer to the surface of the semiconductor material than the first level.Type: ApplicationFiled: February 9, 2018Publication date: July 4, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael Violette, Vladimir Mikhalev
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Patent number: 9991210Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: GrantFiled: July 25, 2016Date of Patent: June 5, 2018Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Publication number: 20160336276Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 9406623Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: GrantFiled: October 6, 2014Date of Patent: August 2, 2016Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 9337333Abstract: A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.Type: GrantFiled: July 31, 2014Date of Patent: May 10, 2016Assignee: Micron Technology, Inc.Inventors: Michael Smith, Vladimir Mikhalev, Puneet Sharma, Zia Alan Shafi, Henry Jim Fulford
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Patent number: 9287260Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.Type: GrantFiled: September 5, 2014Date of Patent: March 15, 2016Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Vladimir Mikhalev
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Publication number: 20160071842Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.Type: ApplicationFiled: September 5, 2014Publication date: March 10, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Smith, Vladimir Mikhalev
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Publication number: 20150021707Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: ApplicationFiled: October 6, 2014Publication date: January 22, 2015Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 8906771Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.Type: GrantFiled: September 4, 2012Date of Patent: December 9, 2014Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
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Publication number: 20140339648Abstract: A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael Smith, Vladimir Mikhalev, Puneet Sharma, Zia Alan Shafi, Henry Jim Fulford
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Patent number: 8853833Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: GrantFiled: June 13, 2011Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 8815667Abstract: Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.Type: GrantFiled: December 16, 2009Date of Patent: August 26, 2014Assignee: Micron Technology, Inc.Inventors: Michael Smith, Vladimir Mikhalev, Puneet Sharma, Zia Alan Shafi, Henry Jim Fulford
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Publication number: 20120329231Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
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Publication number: 20120313691Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.Type: ApplicationFiled: June 13, 2011Publication date: December 13, 2012Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
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Patent number: 8274081Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.Type: GrantFiled: March 22, 2010Date of Patent: September 25, 2012Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
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Patent number: 8243526Abstract: A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.Type: GrantFiled: December 14, 2009Date of Patent: August 14, 2012Assignee: Intel CorporationInventors: Michael Smith, Vladimir Mikhalev, Kenneth Marr, Haitao Liu
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Patent number: 8102709Abstract: Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain region. Such transistors should facilitate a reduction in edge effect and leakage as the channel of the transistor is not bordering on an isolation region. Additionally, the use of a source/drain region extending through a channel region facilitates high-power, high-voltage operation.Type: GrantFiled: June 2, 2009Date of Patent: January 24, 2012Assignee: Micron Technology, Inc.Inventor: Vladimir Mikhalev
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Publication number: 20110227071Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
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Publication number: 20110140227Abstract: A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.Type: ApplicationFiled: December 14, 2009Publication date: June 16, 2011Inventors: Michael A. Smith, Vladimir Mikhalev, Kenneth Marr, Haitao Liu
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Patent number: RE46005Abstract: A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal and a control circuit configured to control the main delay line to vary the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal. The detection circuit is configured to receive the input clock signal and the feedback clock signal, detect a phase alignment error between the input clock signal and the feedback clock signal, and assert the enable signal responsive to the phase alignment error exceeding a predetermined amount.Type: GrantFiled: May 4, 2007Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: Vladimir Mikhalev, Feng Lin