Patents by Inventor Vladimir Odnoblyudov

Vladimir Odnoblyudov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535547
    Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 14, 2020
    Assignee: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
  • Patent number: 10529613
    Abstract: A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 7, 2020
    Assignee: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
  • Patent number: 10510582
    Abstract: A substrate includes a polycrystalline ceramic core; a first adhesion layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesion layer; a second adhesion layer encapsulating the conductive layer; a barrier layer encapsulating the second adhesion layer, and a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 17, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10510577
    Abstract: A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 17, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Publication number: 20190371962
    Abstract: Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.
    Type: Application
    Filed: August 9, 2019
    Publication date: December 5, 2019
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Publication number: 20190371929
    Abstract: A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 5, 2019
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Steve Lester, Ozgur Aktas
  • Patent number: 10490636
    Abstract: A method of forming a semiconductor device includes providing an engineered substrate, forming a gallium nitride layer coupled to the engineered substrate, forming a channel region coupled to the gallium nitride layer by forming an aluminum gallium nitride barrier layer on the front surface of the gallium nitride layer, forming a gate dielectric layer coupled to the aluminum gallium nitride barrier layer in the central portion of the channel region, forming a gate contact coupled to the gate dielectric layer, forming a source contact at the first end of the channel region, forming a via at the second end of the channel region, filling the via with a conductive material, forming a drain contact coupled to the via, removing the engineered substrate to expose the back surface of the epitaxial gallium nitride layer, and forming a drain pad on the back surface of the epitaxial gallium nitride layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 26, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Ozgur Aktas
  • Patent number: 10483481
    Abstract: A vertical solid state lighting (SSL) device is disclosed. In one embodiment, the SSL device includes a light emitting structure formed on a growth substrate. Individual SSL devices can include a embedded contact formed on the light emitting structure and a metal substrate plated at a side at least proximate to the embedded contact. The plated substrate has a sufficient thickness to support the light emitting structure without bowing.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Scott D. Schellhammer
  • Publication number: 20190348275
    Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 10475976
    Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Publication number: 20190341535
    Abstract: Light emitting diode packages as disclosed herein include a monolithic chip including at least a first and a second light emitting diode (LED) that are electrically coupled in series, wherein the first and the second LEDs each include at least one electrical terminal configured to be electrically coupled to a power source. The monolithic chip is mounted onto a connection substrate having first and second landing pads formed from metallic material and electrically isolated from each other. The monolithic chip is mounted to the connection substrate such that the electrical terminal of the first LED is electrically connected to the first landing pad and the electrical terminal of the second LED is electrically connected to the second landing pad. In an example, the monolithic chip includes a third and a fourth LED electrically coupled to each other in series, and electrically coupled to the first and second LEDs in parallel.
    Type: Application
    Filed: March 8, 2019
    Publication date: November 7, 2019
    Inventor: Vladimir A. Odnoblyudov
  • Publication number: 20190341534
    Abstract: Light emitting diode (LED) constructions comprise an LED having a pair of electrical contacts along a bottom surface. A lens is disposed over the LED and covers a portion of the LED bottom surface. A pair of electrical terminals is connected with respective LED contacts, are sized larger than the contacts, and connect with the lens material along the LED bottom surface. A wavelength converting material may be interposed between the LED and the lens. LED constructions may comprise a number of LEDs, where the light emitted by each LED differs from one another by about 2.5 nm or less. LED constructions are made by attaching 2 or more LEDs to a common wafer by adhesive layer, forming a lens on a wafer level over each LED to provide a rigid structure, removing the common wafer, forming the electrical contacts on a wafer level, and then separating the LEDs.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 7, 2019
    Inventors: Vladimir A. Odnoblyudov, R. Scott West
  • Patent number: 10468562
    Abstract: Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength. The structure can further include a second region positioned adjacent to the first region to emit radiation at a second wavelength different than the first wavelength. The second region has a second value of the material characteristic that is different than the first value, with the first and second values of the characteristic forming a potential gradient to drive electrons, holes, or both electrons and holes in the radiative structure from the first region to the second region. In a further particular embodiment, the material characteristic includes material polarization.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Publication number: 20190334015
    Abstract: A vertical Schottky diode includes an ohmic contact, a first epitaxial N-type gallium nitride layer physically contacting the ohmic contact and having a first doping concentration, and a second epitaxial N-type gallium nitride layer physically contacting the first epitaxial N-type gallium nitride layer and having a second doping concentration that is lower than the first doping concentration. The vertical Schottky diode further includes a first edge termination region and a second edge termination region coupled to the second epitaxial N-type gallium nitride layer and separated from each other by a portion of the second epitaxial N-type gallium nitride layer, and a Schottky contact coupled to the portion of the second epitaxial N-type gallium nitride layer, and to the first edge termination region and the second edge termination region.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Ozgur Aktas
  • Patent number: 10461064
    Abstract: Flip chip LEDs comprise a transparent carrier and an active material layer such as AlInGaP bonded to the carrier and that emits light between about 550 to 650 nm. The flip chip LED has a first electrical terminal in contact with a first region of the active material layer, and a second electrical terminal in contact with a second region of the active material layer, wherein the first and second electrical terminals are positioned along a common surface of the active material layer. Chip-on-board LED packages comprise a plurality of the flip chip LEDs with respective first and second electrical terminals interconnected with one another. The package may include Flip chip LEDs that emit light between 420 to 500 nm, and the flip chip LEDs are covered with a phosphorus material comprising a yellow constituent, and may comprise a transparent material disposed over the phosphorus material.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 29, 2019
    Assignee: Bridgelux, Inc.
    Inventor: Vladimir A. Odnoblyudov
  • Publication number: 20190326148
    Abstract: A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
  • Publication number: 20190319179
    Abstract: Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 17, 2019
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Publication number: 20190316742
    Abstract: In various embodiments, lighting systems include a carrier having a plurality of conductive elements disposed thereon and a light-emitting array. The light-emitting array is disposed over the carrier and includes a plurality of light-emitting diodes (LEDs), each of which has at least two electrical contacts electrically connected to conductive elements.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 17, 2019
    Inventors: Michael A. TISCHLER, Vladimir ODNOBLYUDOV, David KEOGH
  • Publication number: 20190312081
    Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.
    Type: Application
    Filed: June 13, 2019
    Publication date: October 10, 2019
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 10438792
    Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 8, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas