Abstract: In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.

Abstract: The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal.

Abstract: The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serialize data communication channel and an input of a deserialize data communication channel to provide a serial data loop-back connection and coupling an output of a deserialize data communication channel and an input of a serialize data communication channel to provide a parallel data loop-back connection.

Abstract: A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.

Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

Abstract: The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling clocks, with these clocks having sampling clock phases separated in time. These clocks are used in conjunction with multiple data detectors and phase detectors to efficiently process received analog signals in a decimated loop filter system.

Abstract: Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.

Abstract: Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.

Abstract: Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.

Abstract: Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.

Abstract: The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros adjacent to one another. Moreover, these internal signal paths permit efficient distribution of a common source signal to each of such connected macros. The layout of the internal macro cell signal paths of the present invention also permits each of these macros to be reflected about its Y-axis, thereby increasing its versatility in being utilized in various circuit designs.

Abstract: Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.

Abstract: Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

Abstract: The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

Abstract: Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. A data stream is received and the phase of a clock signal is adjusted using two interpolators. The data stream is then recovered using the clock signal.

Abstract: A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.

Abstract: A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.