Abstract: The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros adjacent to one another. Moreover, these internal signal paths permit efficient distribution of a common source signal to each of such connected macros. The layout of the internal macro cell signal paths of the present invention also permits each of these macros to be reflected about its Y-axis, thereby increasing its versatility in being utilized in various circuit designs.

Abstract: The present invention provides a low power method and apparatus for detecting a signaling tone. The apparatus comprises a resonator which can be configured to resonate at a specified frequency, a controller for configuring the resonator, and a comparator for comparing the output of the resonator as configured by the controller. The method comprises configuring the resonator to resonate at a first frequency to generate an output, configuring the resonator to resonate at a second frequency to generate an output, comparing the outputs, and indicating the presence of a signal if the output of the resonator configured to resonate at a first frequency exceeds the output of the resonator configured to resonate at a second frequency by a predefined amount.

Abstract: A FIFO is provided which includes gray-encoded READ and WRITE counters in which partial capacity flags (referred to collectively as “WATERMARK level” flags herein) are generated when the difference between the count values in the two counters exceeds a first threshold level and which resets the flag when the difference between the count values drops below a second, lower threshold level. In accordance with the present invention, a single gray-coded WRITE pointer counter comprises a WRITE pointer register and a gray-code increment block. A READ pointer register comprises a shift register and a gray code increment block having plural stages and storing consecutive incremental WATERMARK values, based on the READ pulse count, therein. With each successive READ clock pulse, consecutive WATERMARK values are stored in the plural-stage READ pointer register, and with each READ clock pulse these values are incremented by one.

Abstract: An integrated circuit debugger incorporated into an integrated circuit, allowing direct access to internal points within the integrated circuit. By having direct access to internal points within the integrated circuit, the debugger is capable of faster and more accurate debugging. The debugger is able to directly access internal points of the integrated circuit which were previously inaccessible or only accessible indirectly for debugging, such as memory addresses, memory data, read/write strobes, and internal chip states. In addition, by accessing internal points of the integrated circuits directly, debugging instructions can be performed in real-time with minimal interruption to the operation of the integrated circuit.

Abstract: A method and apparatus which compensates for the effect of DC components due to imperfections in analog circuits used in a coder/decoder (CODEC) by adding a compensation value to an outgoing signal prior to the DC components being introduced. The method includes the steps of determining a compensation value to compensate for the effect of the DC components due to imperfections in analog circuits in a CODEC and adding the compensation value to a path within the CODEC. The apparatus includes an adder coupled in at least one outgoing path of the CODEC, the adder having an input for coupling to a DSP, wherein the DSP determines a DC compensation value to compensate for the effect of the DC components and the adder adds the DC compensation value to the outgoing path.

Abstract: A method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). The accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.

Abstract: A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging mask register selectably disable bits of the memory paging register to redefine the length and physical characteristics of pages in memory based on the needs of a software program. As a result, the paged partitions in memory may be of variable length and/or may comprise non-contiguous portions of the memory.

Abstract: The present invention provides a low power method and apparatus for detecting a signaling tone. The apparatus comprises a resonator which can be configured to resonate at a specified frequency, a controller for configuring the resonator, and a comparator for comparing the output of the resonator as configured by the controller. The method comprises configuring the resonator to resonate at a first frequency to generate an output, configuring the resonator to resonate at a second frequency to generate an output, comparing the outputs, and indicating the presence of a signal if the output of the resonator configured to resonate at a first frequency exceeds the output of the resonator configured to resonate at a second frequency by a predefined amount.

Abstract: A method and apparatus which compensates for the effect of DC components due to imperfections in analog circuits used in a coder/decoder (CODEC) by adding a compensation value to an outgoing signal prior to the DC components being introduced. The method includes the steps of determining a compensation value to compensate for the effect of the DC components due to imperfections in analog circuits in a CODEC and adding the compensation value to a path within the CODEC. The apparatus includes an adder coupled in at least one outgoing path of the CODEC, the adder having an input for coupling to a DSP, wherein the DSP determines a DC compensation value to compensate for the effect of the DC components and the adder adds the DC compensation value to the outgoing path.

Abstract: The invention is a method and apparatus for ensuring synchronization for digital communication between a transmitting and a receiving device, particularly when the clock and/or frame synchronization is sourced from a different location than the transmit data. In accordance with the first aspect of the invention, the transmitting device employs a look ahead algorithm to begin transmitting data before actual receipt of the frame synchronization signal.

Abstract: A flexible memory overlaying apparatus and method stores repeatedly referenced information, e.g, common global variables, common code segments, interrupt service routines, and/or any other user or system definable information, in spare addressable circuits accessed by a memory aliasing or overlaying module. The memory aliasing module monitors (or snoops) memory access by a processor to redirect access to certain appropriate addressable circuits to provide faster access to the information than would be available in an access made from main memory. The memory overlaying apparatus and method provides an efficient context switching, e.g., during an interrupt, enables a reduction in the size of instruction code requirements, and helps avoid the occurrences of cache misses, and/or thrashing between cached pages.

Abstract: An ADSL front end is implemented with an adaptive AM interference canceller to cancel out either a carrier signal of an interfering AM radio signal, or a carrier signal and its sidebands of an interfering AM radio signal, from a received ADSL signal. By canceling an interfering AM radio signal rather than simply filtering out the relevant interfered with frequency band, the interfered with frequency band remains useable for ADSL transmission. In one embodiment, a reference AM radio receiver is either fixedly or adaptively tuned to the carrier frequency of an interfering AM radio station, and the received signal in the frequency band surrounding that carrier frequency is digitized and provided to an adaptive interference canceller. The adaptive interference canceller adaptively adjusts a time delay and phase of the generated AM interference signal to optimize cancellation at a hybrid of the same AM radio signal received as interference over a subscriber line.

Abstract: A frequency divider and method for dividing a clock signal. The frequency divider including a first configurable signal generator, a second configurable signal generator, a data source coupled to the signal generators providing configuration data based on instructions received at an instruction port, a sequencer generating the instructions coupled between the signal generators and the data source and passing the instructions to the instruction port of the data source, and combining logic coupled to the outputs of the signal generators to produce the reduced frequency signal.

Abstract: The present invention provides a dual clock D type flip-flop which outputs an active signal after the occurrence of an event on a first data input line triggered by an edge (e.g., a rising edge) of a first clock signal. Thereafter, the output is unchanged by the state of the first data input line and/or the first clock signal until an event is detected on the second data input line based on a second clock signal. The output remains active until the occurrence of another event on the second data input line triggered by an edge (e.g., a rising edge) of the second clock signal. Thereafter, the output remains unchanged by the state of the first data input line and/or the first clock signal until an event is again detected on the first data input line based on the first clock signal. Thus, the dual clock D type flip-flop operates on two separate clock signals and/or data signals without incurring latencies normally present with prior art circuits.

Abstract: Memory banks are assigned to the memory map of a common processor in an order corresponding to a physical characteristic of the respective memory bank, e.g., a physical distance to the processor and/or an electrical distance to the processor. In this way, the operating frequency of the processor can be increased beyond conventionally guaranteed limits at the expense of abandoning the farthest memory banks when not necessary for a particular application. Similarly, abandonment of the farther memory banks in accordance with the principles of the present invention allows operation of the processing system at higher temperatures and/or lower power voltages. In another embodiment of the present invention, wait states may be added to accesses to the farther memory banks such that the closest memory banks may be operated at the highest possible performance level, e.g., without any wait states.

Abstract: An interlocutor system and method is described that allows for at-speed testing of an embedded microcontroller at the control of an embedded digital signal processor in a system-on-a-chip architecture. The interlocutor system includes a buffer for temporarily storing test program data words output by the DSP and retrieved by the microcontroller being tested and a control circuit for controlling the microcontroller and DSP. The microcontroller, DSP, and interlocutor system are all located on a single integrated circuit.

Abstract: An adaptive addressable circuit redundancy method and apparatus, e.g., an adaptive memory redundancy method and apparatus, utilizes an on-chip processor to test, analyze and reassign spare addressable circuits to replace defective or intermittent addressable circuits. The present invention is applicable both in a manufacturing environment and/or in a field environment wherein the integrated circuit is operational. An adaptive addressable circuit redundancy module intercepts a data path between the on-chip processor and the addressable circuits to reassign defective addresses as necessary to utilize a spare addressable circuit bank. In another embodiment of the present invention, a broadcast write module cuts memory test time almost in half by writing a same data pattern to a significant portion or all of the addressable circuits, e.g., memory, substantially simultaneously.

Abstract: An adaptive addressable circuit redundancy method and apparatus, e.g., an adaptive memory redundancy method and apparatus, utilizes an on-chip processor to test, analyze and reassign spare addressable circuits to replace defective or intermittent addressable circuits. The present invention is applicable both in a manufacturing environment and/or in a field environment wherein the integrated circuit is operational. An adaptive addressable circuit redundancy module intercepts a data path between the on-chip processor and the addressable circuits to reassign defective addresses as necessary to utilize a spare addressable circuit bank. In another embodiment of the present invention, a broadcast write module cuts memory test time almost in half by writing a same data pattern to a significant portion or all of the addressable circuits, e.g., memory, substantially simultaneously.