Abstract: Provided is a method for manufacturing a semiconductor device. The method, in one embodiment, includes calibrating an inspection tool configured to obtain a measurement of a semiconductor feature, including: 1) providing a test structure comprising a substrate having a trench therein, and a post feature located over the substrate adjacent the trench. The post feature, in this embodiment, includes a second layer positioned over a first layer, wherein the first layer has a notch or bulge in a sidewall thereof; 2) finding a location of the notch or bulge relative to a different known point of the test structure using a probe of the inspection tool; and 3) calculating a dimension of the probe using the relative locations of the notch or bulge and the different known point.

Abstract: A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using one of scanning probe microscopy (SPM) or profilometry.

Abstract: A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature disposed adjacent to an outside of a corner feature.

Abstract: A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using one of scanning probe microscopy (SPM) or profilometry.

Abstract: A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using one of scanning probe microscopy (SPM) or profilometry.

Abstract: The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.

Abstract: The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.