Abstract: A method for handling an underflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a first word. A second plurality of signal data is packed into a second memory location so as to form a second word. A bitwise operation is then performed between the first word and the second word to produce a result. The result of the operation is then stored in a k bit memory location so as to form a third word. A bit mask is then obtained by arithmetic shifting the third word right (k-1) bits. The bit mask is then inverted. A logical AND operation is then performed between the inverted bit mask and the result.

Abstract: The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. The data signals are represented as unsigned 8-bit binary values. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a maximum overflow state or a minimum overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is in the maximum or minimum overflow state.

Abstract: The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state.