Abstract: Method for operating a container treatment system (1), wherein containers are treated in a first predefined fashion with a first treatment device (2) of this container treatment system (1), are subsequently transported from this first treatment device (2) to a second treatment device (4) of the container treatment system (1) and are subsequently treated in a second predefined fashion by the second treatment device (4), wherein a first multiplicity of first reference characteristic values (RK1), which are characteristic of the treatment of the containers (10) the first treatment device (2), is recorded by means of first sensor devices (22a, 24a), and a second multiplicity of second reference characteristic values (RK2), which are characteristic of the treatment of the containers (10) with the second treatment device (4), is recorded by means of second sensor devices (42a, 44a), and wherein these reference characteristic values (RK1, RK2) are stored in a memory device (16).

Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.

Abstract: In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Abstract: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

Abstract: A method and apparatus for checking gripping elements for containers may include a plurality of gripping elements for gripping a plurality of containers. Occupancy states of these gripping elements with containers are regularly detected and statistics regarding these occupancy states are formed. Based on these statistics, in particular a failure of individual gripping elements can be ascertained and can be output to the user in a targeted manner.

Abstract: Method for operating a container treatment system (1), wherein containers are treated in a first predefined fashion with a first treatment device (2) of this container treatment system (1), are subsequently transported from this first treatment device (2) to a second treatment device (4) of the container treatment system (1) and are subsequently treated in a second predefined fashion by the second treatment device (4), wherein a first multiplicity of first reference characteristic values (RK1), which are characteristic of the treatment of the containers (10) the first treatment device (2), is recorded by means of first sensor devices (22a, 24a), and a second multiplicity of second reference characteristic values (RK2), which are characteristic of the treatment of the containers (10) with the second treatment device (4), is recorded by means of second sensor devices (42a, 44a), and wherein these reference characteristic values (RK1, RK2) are stored in a memory device (16).

Abstract: A method and apparatus for checking gripping elements for containers may include a plurality of gripping elements for gripping a plurality of containers. Occupancy states of these gripping elements with containers are regularly detected and statistics regarding these occupancy states are formed. Based on these statistics, in particular a failure of individual gripping elements can be ascertained and can be output to the user in a targeted manner.

Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.

Abstract: In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Abstract: An efficient patterning strategy may be applied when etching through a dielectric material system on the basis of two different etch chemistries. To this end, a conductive etch stop or barrier material may be formed in the opening prior to etching through the further dielectric layer of the material system, thereby substantially preserving the initial critical dimensions and avoiding etch damage. Thus, superior contact openings, via openings and the like may be formed on the basis of well-established etch chemistries.

Abstract: Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.

Abstract: By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects.

Abstract: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

Abstract: A method and apparatus for checking gripping elements for containers may include a plurality of gripping elements for gripping a plurality of containers. Occupancy states of these gripping elements with containers are regularly detected and statistics regarding these occupancy states are formed. Based on these statistics, in particular a failure of individual gripping elements can be ascertained and can be output to the user in a targeted manner.

Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Abstract: By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects.

Abstract: Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.

Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Abstract: In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the passivation layer. An etching process adapted to remove a material of the passivation layer is performed and the mask is removed. Then, a second etching process adapted to remove residues of the passivation layer from the contact pad can be performed. The removal of the mask may be performed at a temperature of the substrate in a range from about ?20° C. to about 100° C. The second etching process can comprise exposing the substrate to a gaseous etchant comprising hydrogen and fluorine, an amount of hydrogen in the etchant being about equal to an amount of fluorine, or greater. Thus, a formation of oxides and/or fluorides on the at least one contact pad can be avoided.

Abstract: In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the passivation layer. An etching process adapted to remove a material of the passivation layer is performed and the mask is removed. Then, a second etching process adapted to remove residues of the passivation layer from the contact pad can be performed. The removal of the mask may be performed at a temperature of the substrate in a range from about ?20° C. to about 100° C. The second etching process can comprise exposing the substrate to a gaseous etchant comprising hydrogen and fluorine, an amount of hydrogen in the etchant being about equal to an amount of fluorine, or greater. Thus, a formation of oxides and/or fluorides on the at least one contact pad can be avoided.