Abstract: A layer is structured by first applying a sacrificial layer on the layer to be structured, forming a mask with an inorganic material on the sacrificial layer, then patterning the sacrificial layer and the layer to be structured through the mask, and, finally, removing the sacrificial layer and the mask.

Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.

Abstract: The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches.

Abstract: A method for producing structures having a high aspect ratio includes the following steps: a material of the structure to be produced is provided in the form of a layer, a mask is applied to the layer, the layer is subjected to dry etching using the mask, thereby forming redepositions of the layer material on side walls of the mask and the mask is removed, so that a structure having a high aspect ratio is left behind. The method enables very high (≧1 &mgr;m) and very thin (≦50 nm) structures to be produced in a relatively simple and rapid manner in only very few process steps and with only one mask technique. Structures having such large aspect ratios, particularly when they are composed of a conductive material, cannot be produced, or can be produced only with a high outlay, by using other methods.

Abstract: A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

Abstract: A method for producing a noble metal-containing structure on a substrate, and a semiconductor component having such a noble metal-containing structure, include introducing a noble metal into a preliminary structure by converting a gaseous compound of the noble metal with a non-noble metal in a preliminary structure into elementary noble metal and a gaseous compound of the non-noble metal. The process continues until a desired amount of the non-noble metal in the preliminary structure is replaced by the noble metal.

Abstract: A raised basic structure is first made from a conducting or nonconducting, easily structurable substitute material. Electrode material, such as platinum, is then sputtered onto the basic structure. The layer thickness of the electrode material is greater on the surface and on the side walls of the basic structure than on the neighbouring surface. After a subsequent anisotropic etching process, the electrode material remains only on the basic structure, including the top surface and the side walls. The process is applicable to memory cells having a capacitor dielectric with a high-.epsilon.-dielectric or ferroelectric material.