Patents by Inventor Volodymyr SHVYDUN

Volodymyr SHVYDUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973517
    Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 30, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventor: Volodymyr Shvydun
  • Publication number: 20240063940
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 22, 2024
    Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
  • Patent number: 11902721
    Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 13, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Whay Sing Lee, Arash Farhoodfar, Volodymyr Shvydun, Michael Duckering
  • Publication number: 20230421180
    Abstract: A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive blocks of data defining symbol blocks that are encoded using a block code to correct an error in a block of data and to interleave the symbol blocks into a stream of interleaved symbol blocks. The encoder is configured to encode a set of symbol blocks among the interleaved symbol blocks with an error-correcting code to correct single bit errors in the set of symbol blocks. The error-correcting code is configured to generate an error-correcting block and to add the error-correcting block to the set of interleaved symbol blocks.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Benjamin P. SMITH, Volodymyr Shvydun, Jamal Riani, Ilya Lyubomirsky
  • Patent number: 11804925
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: October 31, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
  • Publication number: 20230327806
    Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Jamal RIANI, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
  • Patent number: 11764811
    Abstract: A communication device includes interleaver circuitry that receives, from a host device, a first encoded data stream comprised of a plurality of symbols encoded with a first type of error correction code and interleaves the plurality of symbols of the first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. Encoder circuitry encodes the first encoded data stream in accordance with a second type of error correction code different from the first type of error correction code by generating, for each of the symbol sections, an error code block corresponding to the symbols in the symbol section and outputs a second encoded data stream including the first encoded data stream and the error code block.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: September 19, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Benjamin P. Smith, Volodymyr Shvydun, Jamal Riani, Ilya Lyubomirsky
  • Patent number: 11683124
    Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: June 20, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
  • Publication number: 20220302930
    Abstract: A communication device includes interleaver circuitry that receives, from a host device, a first encoded data stream comprised of a plurality of symbols encoded with a first type of error correction code and interleaves the plurality of symbols of the first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. Encoder circuitry encodes the first encoded data stream in accordance with a second type of error correction code different from the first type of error correction code by generating, for each of the symbol sections, an error code block corresponding to the symbols in the symbol section and outputs a second encoded data stream including the first encoded data stream and the error code block.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Benjamin P. SMITH, Volodymyr SHVYDUN, Jamal RIANI, Ilya LYUBOMIRSKY
  • Publication number: 20220224997
    Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.
    Type: Application
    Filed: March 2, 2022
    Publication date: July 14, 2022
    Inventors: Whay Sing LEE, Arash FARHOODFAR, Volodymyr SHVYDUN, Michael DUCKERING
  • Publication number: 20220201225
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 23, 2022
    Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
  • Publication number: 20220182078
    Abstract: The present invention is directed to data communication systems and methods thereof According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventor: Volodymyr SHVYDUN
  • Patent number: 11356122
    Abstract: A communication device includes a first alignment circuit configured to receive, from a host device, a first encoded data stream including a plurality of symbols encoded with a first type of error correction code. The first alignment circuit is configured to output an aligned first encoded data stream that is aligned to boundaries between the plurality of symbols encoded with the first type of error correction code. An interleaver is configured to interleave the plurality of symbols of the aligned first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. An encoder is configured to generate, for each of the symbol sections, a parity block corresponding to the symbols in the symbol section and to output a second encoded data stream including the aligned first encoded data stream and the parity block.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Benjamin Smith, Volodymyr Shvydun, Jamal Riani, Ilya Lyubomirsky
  • Publication number: 20220173833
    Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 2, 2022
    Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Srinivas SWAMINATHAN, Arash FARHOODFAR
  • Patent number: 11277224
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 15, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
  • Patent number: 11272270
    Abstract: The present invention is direct to data communication. In a specific embodiment, multiple independent data streams, which are at a first data rate, are transcoded by separate communication pipelines into data blocks. The data blocks, associated with these separate and independent data streams, are multiplexed with alignment markers to generate an output data stream. The output data stream is transmitted at a second data rate, which is higher than the first data rate.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: March 8, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Whay Sing Lee, Arash Farhoodfar, Volodymyr Shvydun, Michael Duckering
  • Publication number: 20220070556
    Abstract: The present invention is direct to data communication. In a specific embodiment, multiple independent data streams, which are at a first data rate, are transcoded by separate communication pipelines into data blocks. The data blocks, associated with these separate and independent data streams, are multiplexed with alignment markers to generate an output data stream. The output data stream is transmitted at a second data rate, which is higher than the first data rate.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 3, 2022
    Inventors: Whay Sing LEE, Arash FARHOODFAR, Volodymyr SHVYDUN, Michael DUCKERING
  • Patent number: 11265109
    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 1, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
  • Patent number: 11265025
    Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 1, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventor: Volodymyr Shvydun
  • Publication number: 20210288672
    Abstract: The present invention is directed to data communication and encoding techniques. More specifically, an embodiment of the present invention provides a communication device that aligns a data stream with RS symbols. An interleaver interleaves RS symbols to generate an interleaved RS symbol data stream. Hamming parity blocks are generated for corresponding groups of RS symbols and inserted into the interleaved RS symbol data stream. There are other embodiments as well.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Benjamin SMITH, Volodymyr SHVYDUN, Jamal RIANI, ILya LYUBOMIRSKY