Patents by Inventor Volodymyr SHVYDUN
Volodymyr SHVYDUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200343999Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
-
Patent number: 10749629Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: GrantFiled: May 3, 2019Date of Patent: August 18, 2020Assignee: INPHI CORPORATIONInventors: Jamal Riani, Benjamin P. Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
-
Publication number: 20200228146Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventor: Volodymyr SHVYDUN
-
Publication number: 20200220659Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Srinivas SWAMINATHAN, Arash Farhoodfar
-
Patent number: 10651874Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.Type: GrantFiled: November 15, 2018Date of Patent: May 12, 2020Assignee: INPHI CORPORATIONInventor: Volodymyr Shvydun
-
Publication number: 20190268091Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: ApplicationFiled: May 3, 2019Publication date: August 29, 2019Inventors: Jamal RIANI, Benjamin P. SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
-
Patent number: 10326550Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: GrantFiled: August 30, 2017Date of Patent: June 18, 2019Assignee: INPHI CORPORATIONInventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja
-
Publication number: 20190089385Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.Type: ApplicationFiled: November 15, 2018Publication date: March 21, 2019Inventor: Volodymyr SHVYDUN
-
Patent number: 10158379Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.Type: GrantFiled: September 30, 2016Date of Patent: December 18, 2018Assignee: INPHI CORPORATIONInventor: Volodymyr Shvydun
-
Publication number: 20170026058Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Inventor: Volodymyr SHVYDUN
-
Patent number: 9484960Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.Type: GrantFiled: January 21, 2015Date of Patent: November 1, 2016Assignee: INPHI CORPORATIONInventor: Volodymyr Shvydun
-
Patent number: 9385893Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.Type: GrantFiled: February 10, 2014Date of Patent: July 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey
-
Patent number: 9304535Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.Type: GrantFiled: March 21, 2014Date of Patent: April 5, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa, Hiep T. Pham
-
Patent number: 9215106Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.Type: GrantFiled: March 21, 2014Date of Patent: December 15, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Adam B. Healey, Hiep T. Pham, Volodymyr Shvydun
-
Publication number: 20150256363Abstract: An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.Type: ApplicationFiled: March 27, 2014Publication date: September 10, 2015Applicant: LSI CorporationInventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa
-
Patent number: 9130797Abstract: An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.Type: GrantFiled: May 1, 2014Date of Patent: September 8, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Chaitanya Palusa, Volodymyr Shvydun, Hiep T. Pham, Adam B. Healey
-
Publication number: 20150236875Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.Type: ApplicationFiled: March 21, 2014Publication date: August 20, 2015Applicant: LSI CorporationInventors: Chaitanya Palusa, Adam B. Healey, Hiep T. Pham, Volodymyr Shvydun
-
Publication number: 20150234423Abstract: Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.Type: ApplicationFiled: March 21, 2014Publication date: August 20, 2015Applicant: LSI CorporationInventors: Volodymyr Shvydun, Adam B. Healey, Chaitanya Palusa, Hiep T. Pham
-
Publication number: 20150207648Abstract: Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.Type: ApplicationFiled: February 10, 2014Publication date: July 23, 2015Applicant: LSI CorporationInventors: Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey
-
Patent number: 9077574Abstract: A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.Type: GrantFiled: March 27, 2014Date of Patent: July 7, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Adam B. Healey, Chaitanya Palusa, Tomasz Prokop, Volodymyr Shvydun