Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

Abstract: An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.

Abstract: An apparatus of a computing system, a computer-readable medium, a method and a system. The apparatus comprises an input/output interface and one or more processors connected to the input/output interface and adapted to perform a first reading of first fuse data stored in a fuse array storage circuitry to result in read first fuse data, and receive the read first fuse data from the fuse array storage circuitry through the input/output interface; after a random time-delay, perform a second reading of second fuse data stored in the fuse array storage circuitry to result in read second fuse data, and receive the read second fuse data from the fuse array storage circuitry through the input/output interface; and compare the read first fuse data with the read second fuse data, and if there is no match, halt a boot-up of the computing system.

Abstract: An apparatus of a computing system, a computer-readable medium, a method and a system. The apparatus comprises an input/output interface and one or more processors connected to the input/output interface and adapted to perform a first reading of first fuse data stored in a fuse array storage circuitry to result in read first fuse data, and receive the read first fuse data from the fuse array storage circuitry through the input/output interface; after a random time-delay, perform a second reading of second fuse data stored in the fuse array storage circuitry to result in read second fuse data, and receive the read second fuse data from the fuse array storage circuitry through the input/output interface; and compare the read first fuse data with the read second fuse data, and if there is no match, halt a boot-up of the computing system.

Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.

Abstract: Methods and apparatus for managing sideband segments in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF includes a plurality of segments that may be reset or powered down independently after power management logic determines that in progress messages have been handled and future messages to the segment being reset or powered down will be blocked. Other embodiments are also disclosed.

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.

Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.

Abstract: A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.

Abstract: A system and apparatus combining a hub and a function as a single chip compound device. A single serial interface engine (SIE) is shared between a hub endpoint and a function endpoint. The hub endpoint and function endpoint being integrated on a single chip. A single backend interface is coupled between the SIE and the endpoints. The backend interface selects which of the hub endpoints or the function endpoints can access the shared SIE at any time period. In one embodiment, a first address is associated with the hub and a second address is associated with the function. The backend interface selects between the hub and function by comparing a translated address received from the SIE with each of the first address and the second address. The result of the comparisons via suitable combinational logic serves as a select signal for a multiplexer between the hub/function and the SIE.