Abstract: A method and apparatus for generating both a uniform duty cycle clock and a variable duty cycle clock with a single state machine. A single state machine is provided having a series of states through which it transitions when in a first mode. The series of states causes the output of the state machine to be a uniform duty cycle clock signal. The state machine has a second group of states through which it transitions in a second mode. A transition scheme among the second group of states permits the duty cycle of a state machine output clock signal to vary.

Abstract: An apparatus and method of reducing power consumption in an integrated device having a first module with a mandatory operating frequency and a second module with a flexible frequency requirement. The integrated device is powered by a serial bus. The first module is segregated from the second module in the time domain by a frequency independent interface. The second module is then operated at a lower frequency when power conservation is needed. The operating frequency of the second module can be dynamically changed to improve performance of the second module when a power budget for the device permits.

Abstract: A clock and reset unit for providing power saving modes to a pipelined microprocessor and for guaranteeing that power saving instruction is the last to be executed before the clocks stop, upon wake-up the next instruction executed is the first instruction in the interrupt service routine (ISR) and that upon return from the ISR, the instruction immediately following the power saving instruction is executed. A register is provided in the clock and reset unit for initiating a power saving mode. A software programmer selects a particular power saving mode by setting a corresponding bit in this register (i.e., writing a predetermined value to this register). A processor stalling signal generator for generating a signal that indicates to the processor that the peripheral is not ready to process a processor request (thereby causing the processor to insert wait states until the peripheral is ready) is provided.