Abstract: A register rename unit employs a rename map stack upon which a register rename map corresponding to each dispatched instruction is pushed. Upon occurrence of an exception, the register rename maps corresponding to instructions subsequent to the instruction experiencing the exception are popped from the stack. In this manner, the architected register to implemented register mapping consistent with the instruction experiencing the exception is restored. According to one embodiment, the rename map stack can be recovered from an exception in one clock cycle. In one particular implementation, the rename map stack comprises multiple independent stacks. Each independent stack corresponds to one of the architected registers, and stores implemented register specifiers corresponding to that architected register.

Abstract: A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding operands. When instructions are presented to the reorder buffer for storage and dependency checking, the reorder buffer allocates storage for the instructions and corresponding instruction results. If an unresolved dependency is detected, the instructions remain stored in the reorder buffer but operand forwarding is delayed until the unresolved dependency becomes resolved. Advantageously, the previously included extra storage and multiplexing prior to dependency checking may be eliminated. Additional clock cycle time may be available for performing dependency checking. Additionally, area formerly occupied by the extra storage is freed for other purposes.

Abstract: A reorder buffer including a speculative storage section and a retired storage section is provided. The speculative storage section stores speculative register states; while the retired storage section stores committed register states corresponding to the execution of instructions which have been retired. The dependency checking logic of the reorder buffer checks dependencies for operands of instructions being dispatched against both the speculative and retired storage sections. In this manner, a dependency is always detected within the reorder buffer. Therefore, no selection between a register file value and a value provided from the reorder buffer need be made. In fact, the register file may be eliminated from a microprocessor employing the reorder buffer. The retired storage section comprises a shiftable queue in one embodiment. The shiftable queue stores committed register states and indications of the architected registers corresponding to the committed register states.

Abstract: This invention provides a hook setting device which uses levers to provide the desired force multiplication factor and force pattern to a fishing line where the force is supplied by one or a combination of tension or compression force means. A trigger means and cautilevered weight of the apparatus provides an initial force or resistance to set the hook in the fish and the levers and force means maintain a preselected force pattern and intensity on the fishing cord.