Abstract: A method for provisioning swap spaces. The method includes: receiving, from a platform orchestrator of a service delivery platform and directed to provisioning a swap space, a swap space instruction specifying a swap space owner and a swap space size; requesting, from the platform orchestrator in response to receiving the swap space instruction and subsequently receiving, a swap space configuration associated with the swap space; based on at least a portion of the swap space configuration: selecting, at least based on the swap space size, at least one physical memory device; creating at least one volume on the at least one physical memory device; creating an emulated memory drive using the at least one volume; and presenting, to the swap space owner, the emulated memory drive as attached swap space representing the swap space.

Abstract: A method for provisioning swap spaces. The method includes: receiving, from a platform orchestrator of a service delivery platform and directed to provisioning a swap space, a swap space instruction specifying a swap space owner and a swap space size; requesting, from the platform orchestrator in response to receiving the swap space instruction and subsequently receiving, a swap space configuration associated with the swap space; based on at least a portion of the swap space configuration: selecting, at least based on the swap space size, at least one physical memory device; creating at least one volume on the at least one physical memory device; creating an emulated memory drive using the at least one volume; and presenting, to the swap space owner, the emulated memory drive as attached swap space representing the swap space.

Abstract: An information handling system may include at least one processor; and an information handling resource, wherein the information handling resource has hardware definition information associated therewith, and wherein the hardware definition information is not stored in a physical storage resource of the information handling resource; wherein the information handling system is configured to: determine a storage location of a database including the hardware definition information of the information handling resource; and retrieve the hardware definition information from the database.

Abstract: An information handling system may include at least one processor; and an information handling resource, wherein the information handling resource has hardware definition information associated therewith, and wherein the hardware definition information is not stored in a physical storage resource of the information handling resource; wherein the information handling system is configured to: determine a storage location of a database including the hardware definition information of the information handling resource; and retrieve the hardware definition information from the database.

Abstract: An information handling system may include at least one processor; and an information handling resource, wherein the information handling resource has hardware definition information associated therewith, and wherein the hardware definition information is not stored in a physical storage resource of the information handling resource; wherein the information handling system is configured to: determine a storage location of a database including the hardware definition information of the information handling resource; and retrieve the hardware definition information from the database.

Abstract: An information handling system includes first and second lines of a differential pair. A baseboard management controller (BMC) periodically determines a resistance of the first line and a resistance of the second line. If the first resistance is substantially equal to the second resistance, then the BMC provides a corrosion signal to a remote diagnostic system.

Abstract: An information handling system includes a power supply and a baseboard management controller (BMC). The power supply includes an input power monitor module and a communication interface. The input power monitor module is configured to detect a total harmonic distortion (THD) on a power input to the power supply, to determine that the THD is greater than a THD threshold, and to provide an indication that the THD is greater than the THD threshold on the communication interface. The BMC is coupled to the communication interface, and is configured to receive the first indication and to enter an item into a log of the information handling system in response to receiving the indication.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica

Abstract: An information handling system includes a current detector module and a baseboard management controller (BMC). The current detector module is configured to detect current slew-rate for an element of the information handling system, to determine that the current slew-rate is greater than a current slew-rate threshold, and to provide an indication that the current slew-rate is greater than the current slew-rate threshold on a communication interface. The BMC may enter an item into a log of the information handling system in response to receiving an indication.

Abstract: In one or more embodiments, an information handling system (IHS) may receive, from another IHS via a first network, a dynamic host configuration protocol discovery request, provide, via the first network, a first Internet protocol version four (IPv4) address to the other IHS, and associate a first Internet protocol version six (IPv6) address. The IHS may receive a domain name service (DNS) lookup request from the first information handling system, provide a multicast DNS (mDNS) request, based at least on logical name information from the DNS lookup request, to a second network, and receive a mDNS response that includes a second IPv6 address associated with the logical name information from the DNS lookup request. In response to receiving the mDNS response, the IHS may configure at least one network address translation configuration that associates that associates the second IPv6 address and a second IPv4 address.

Abstract: An information handling system includes a power supply and a baseboard management controller (BMC). The power supply includes an input power monitor module and a communication interface. The input power monitor module is configured to detect a total harmonic distortion (THD) on a power input to the power supply, to determine that the THD is greater than a THD threshold, and to provide an indication that the THD is greater than the THD threshold on the communication interface. The BMC is coupled to the communication interface, and is configured to receive the first indication and to enter an item into a log of the information handling system in response to receiving the indication.

Abstract: An information handling system includes a current detector module and a baseboard management controller (BMC). The current detector module is configured to detect current slew-rate for an element of the information handling system, to determine that the current slew-rate is greater than a current slew-rate threshold, and to provide an indication that the current slew-rate is greater than the current slew-rate threshold on a communication interface. The BMC may enter an item into a log of the information handling system in response to receiving an indication.

Abstract: An information handling system includes a first processor core that receives a first System Management Interrupt (SMI) event, and synchronizes entry into a System Management Mode (SMM) with second and third processor cores. In response to the first, second, and third processor cores being in the SMM, the first processor executes a first SMI handler to service the first SMI. While the first, second, and third processor core are in the SMM, the second processor core monitors for a high priority SMI event. In response to a detection of the high priority SMI event, the second processor core executes a second SMI handler to service the high priority SMI event.

Abstract: An information handling system includes first and second lines of a differential pair. A baseboard management controller (BMC) periodically determines a resistance of the first line and a resistance of the second line. If the first resistance is substantially equal to the second resistance, then the BMC provides a corrosion signal to a remote diagnostic system.

Abstract: A system includes servers that are connected in series, and a top of rack (TOR) switch having a first TOR switch port and a second TOR switch port that are connected to a first end and a second end, respectively, of the series connected servers. A multi chassis link aggregation group may be established on the first TOR switch port and the second TOR switch port to transform the series connected servers into a single logical channel. A highest media access control address is determined from the servers to represent the single logical channel.

Abstract: An information handling system includes a processor and memory devices that each include a voltage regulator configured to be enabled by a command from the processor. The processor boots the information handling system, including providing the command to the memory devices, and detects that one of the memory devices failed to boot. The processor determines that it is unknown whether the failing memory device is the first memory device or the second memory device. In response, the processor determines which one of the memory devices failed to boot, by rebooting the information handling system, providing a command to a selected one of the memory devices, and determining whether or not the selected one of the memory devices failed to boot.

Abstract: In one or more embodiments, a device may include and/or implement a physical function and multiple virtual functions that are operable to be arranged in a logical nested hierarchy and operable to be configured to respective virtual machines in a hierarchy of nested virtual machines. For example, the physical function may be configured to receive a request, issued from a virtual function of the multiple virtual functions corresponding to a Nth level of nesting of the multiple virtual functions. Until a response to the request is received, the physical function may iteratively provide the request to a virtual function of the multiple virtual functions corresponding to a current level of nesting and if the response to the request is not received from the virtual function corresponding to the current level of nesting, utilize the current level of nesting as a level immediately below the current level of nesting.

Abstract: A system includes servers that are connected in series, and a top of rack (TOR) switch having a first TOR switch port and a second TOR switch port that are connected to a first end and a second end, respectively, of the series connected servers. A multi chassis link aggregation group may be established on the first TOR switch port and the second TOR switch port to transform the series connected servers into a single logical channel. A highest media access control address is determined from the servers to represent the single logical channel.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica