Patents by Inventor Wade Andrew Butcher

Wade Andrew Butcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200029425
    Abstract: A differential pair group equalization system includes a board providing a differential trace pair group with a plurality of differential trace pairs, each of a transmitter device and a receiver device are coupled to the board and the differential trace pairs in the differential trace pair group. At least one of the transmitter device and the receiver device operates to identify a first differential trace pair in the differential trace pair group, and adjust second differential trace pair equalization parameters for a second differential trace pair in the differential trace pair group. If it is determined that first differential trace pair signal transmission capabilities for the first differential trace pair have improved in response to the adjustment of the second differential trace pair equalization parameters for the second differential trace pair the second differential trace pair equalization parameters are set for the second differential trace pair.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 23, 2020
    Inventors: Wade Andrew Butcher, Bhyrav M. Mutnury
  • Publication number: 20190340060
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.
    Type: Application
    Filed: May 5, 2018
    Publication date: November 7, 2019
    Applicant: Dell Products L.P.
    Inventors: Vijay Bharat NIJHAWAN, Wade Andrew BUTCHER, Vadhiraj SANKARANARAYANAN
  • Publication number: 20190236029
    Abstract: An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Applicant: Dell Products L.P.
    Inventors: Wade Andrew BUTCHER, Vadhiraj SANKARANARAYANAN, Stuart Allen BERKE
  • Publication number: 20190227969
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Applicant: Dell Products L.P.
    Inventors: Wade Andrew BUTCHER, Sandor FARKAS
  • Patent number: 10360167
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 23, 2019
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Sandor Farkas
  • Patent number: 10356015
    Abstract: In one or more embodiments, one or more systems, processes, and/or methods may utilize a trace unit that stores trace data via a trace buffer in a memory medium and may utilize a network interface that provides the trace data from the trace buffer to a network. In one example, the network interface may provide the trace data from the trace buffer to the network in response to a trigger. In one instance, the trigger may include a modification of a pointer to an address of the trace buffer. In another instance, the trigger may include an expiration of a timer. In another example, the trace unit may filter the trace data. In one or more embodiments, storing the traced data and providing the trace data to the network may be performed without involving a main processor of an information handling system that includes the trace unit.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Kurtis John Bowman
  • Publication number: 20190132283
    Abstract: In one or more embodiments, an information handling system (IHS) may receive, from another IHS via a first network, a dynamic host configuration protocol discovery request, provide, via the first network, a first Internet protocol version four (IPv4) address to the other IHS, and associate a first Internet protocol version six (IPv6) address. The IHS may receive a domain name service (DNS) lookup request from the first information handling system, provide a multicast DNS (mDNS) request, based at least on logical name information from the DNS lookup request, to a second network, and receive a mDNS response that includes a second IPv6 address associated with the logical name information from the DNS lookup request. In response to receiving the mDNS response, the IHS may configure at least one network address translation configuration that associates that associates the second IPv6 address and a second IPv4 address.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Lee E. Ballard, Wade Andrew Butcher
  • Patent number: 10164909
    Abstract: A network adapter, includes a first transceiver module with a transceiver that operates according to a first network protocol and a memory element that includes information that identifies the first network protocol, a second transceiver module with a transceiver that operates according to a second network protocol and a memory element that includes information that identifies the second network protocol, and a controller that reads the information from the first memory element, directs an information handling system to invoke a first network driver associated with the first network protocol based upon the information, reads the second information from the second memory element, and directs the information handling system to invoke a second network driver associated with the second network protocol based upon the second information.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 25, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Jonathan F. Lewis, Hendrich M. Hernandez, Wade Andrew Butcher, Kevin A. Hughes
  • Publication number: 20180357091
    Abstract: In one or more embodiments, a device may include and/or implement a physical function and multiple virtual functions that are operable to be arranged in a logical nested hierarchy and operable to be configured to respective virtual machines in a hierarchy of nested virtual machines. For example, the physical function may be configured to receive a request, issued from a virtual function of the multiple virtual functions corresponding to a Nth level of nesting of the multiple virtual functions. Until a response to the request is received, the physical function may iteratively provide the request to a virtual function of the multiple virtual functions corresponding to a current level of nesting and if the response to the request is not received from the virtual function corresponding to the current level of nesting, utilize the current level of nesting as a level immediately below the current level of nesting.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventors: Wade Andrew Butcher, Lee E. Ballard
  • Patent number: 10152264
    Abstract: A memory device update system includes a computing device couple to a management device. While the computing device is in a pre-boot environment, a memory device update engine in the computing device assigns a memory type, which is associated with the storage of memory device update information, to memory region(s) in a memory subsystem in the computing device. Subsequent to a boot of the computing device such that the computing device is in a runtime environment, the memory device update engine retrieves memory device update information from the management device and uses a data communication interface between the memory device update engine and the memory subsystem to write the memory device update information to the memory region(s) that were assigned the memory type. While the computing device is in the runtime environment, the memory subsystem then uses the memory device update information to update the memory subsystem.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 11, 2018
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Vijay Bharat Nijhawan, Vadhiraj Sankaranarayanan
  • Publication number: 20180316629
    Abstract: In one or more embodiments, one or more systems, processes, and/or methods may utilize a trace unit that stores trace data via a trace buffer in a memory medium and may utilize a network interface that provides the trace data from the trace buffer to a network. In one example, the network interface may provide the trace data from the trace buffer to the network in response to a trigger. In one instance, the trigger may include a modification of a pointer to an address of the trace buffer. In another instance, the trigger may include an expiration of a timer. In another example, the trace unit may filter the trace data. In one or more embodiments, storing the traced data and providing the trace data to the network may be performed without involving a main processor of an information handling system that includes the trace unit.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 1, 2018
    Inventors: Wade Andrew Butcher, Kurtis John Bowman
  • Patent number: 10115375
    Abstract: A method may include in response to determining a host system is off, configuring a video controller of an information handling system including setting a display resolution of the video controller and writing management video data associated to a primary frame buffer such that management video data is able to be retrieved by the video controller for output to one or both of a first display associated with the host system and a second display of a management interface communicatively coupled to a management controller communicatively coupled to the processor and the memory and configured to provide out-of-band management of the information handling system. The method may further include in response to determining the host system is on, writing the management video data to an alternate frame buffer such that management video data is able to be retrieved by the video controller for output to the second display.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 30, 2018
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Timothy M. Lambert, Johan Rahardjo
  • Patent number: 10038705
    Abstract: A method and information handling system (IHS) for identifying communication threats in an IHS. The method includes triggering a board management controller (BMC) to transmit a plurality of memory addresses identifying where a plurality of network packets received by the IHS are stored. A field programmable gate array (FPGA) within a processor receives the memory addresses of the network packets and retrieves the network packets. The network packets are analyzed by comparing at least one threat signature that is associated with undesired network behavior with the contents of the network packets. In response to the at least one threat signature matching the contents of at least one of the network packets, an intrusion alert is transmitted to the BMC.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 31, 2018
    Assignee: Dell Products, L.P.
    Inventors: Elie Antoun Jreij, Chitrak Gupta, Wade Andrew Butcher, Sushma Basavarajaiah, Rama Rao Bisa
  • Patent number: 9891678
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a management controller communicatively coupled to the processor and configured to provide out-of-band management of the information handling system, and one or more logic devices. The one or more logic devices may be configured to monitor a power-over-Ethernet input of a network interface communicatively coupled to the one or more logic devices in order to detect an indication at the power-over-Ethernet input of a request to remotely reset the management controller and, responsive to determining presence of the indication at the power-over-Ethernet input of the request to remotely reset the management controller, cause a reset of the management controller.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: February 13, 2018
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Timothy M. Lambert
  • Patent number: 9886568
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a network interface communicatively coupled to the processor, a management controller communicatively coupled to the processor and configured to provide management of the information handling system via a communications channel physically isolated from the network interface, and a controller. The controller may be configured to filter for a packet indicative of a request to remotely reset the management controller and, in response to receiving the packet indicative of the request to remotely reset the management controller, perform a reset of the management controller.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 6, 2018
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Elie Antoun Jreij, Timothy M. Lambert, Hendrich M. Hernandez
  • Patent number: 9710341
    Abstract: Embodiments of systems and methods for fault tolerant link width maximization in a data bus are described. Embodiments of methods may include checking a data bus connection to determine if a degraded lane exists on the data bus, determining a first set of one or more lanes that contain the degraded lane, and assigning a second set of lanes for operation, wherein the second set of lanes does not contain the degraded lane.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: July 18, 2017
    Assignee: DELL PRODUCTS L.P.
    Inventors: Wade Andrew Butcher, Hendrich M. Hernandez, Timothy M. Lambert
  • Publication number: 20170140739
    Abstract: A method may include in response to determining a host system is off, configuring a video controller of an information handling system including setting a display resolution of the video controller and writing management video data associated to a primary frame buffer such that management video data is able to be retrieved by the video controller for output to one or both of a first display associated with the host system and a second display of a management interface communicatively coupled to a management controller communicatively coupled to the processor and the memory and configured to provide out-of-band management of the information handling system. The method may further include in response to determining the host system is on, writing the management video data to an alternate frame buffer such that management video data is able to be retrieved by the video controller for output to the second display.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Applicant: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Timothy M. Lambert, Johan Rahardjo
  • Publication number: 20170123468
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a management controller communicatively coupled to the processor and configured to provide out-of-bound management of the information handling system, and one or more logic devices. The one or more logic devices may be configured to monitor a power-over-Ethernet input of a network interface communicatively coupled to the one or more logic devices in order to detect an indication at the power-over-Ethernet input of a request to remotely reset the management controller and, responsive to determining presence of the indication at the power-over-Ethernet input of the request to remotely reset the management controller, cause a reset of the management controller.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 4, 2017
    Inventors: Wade Andrew Butcher, Timothy M. Lambert
  • Publication number: 20170104770
    Abstract: A method and information handling system (IHS) for identifying communication threats in an IHS. The method includes triggering a board management controller (BMC) to transmit a plurality of memory addresses identifying where a plurality of network packets received by the IHS are stored. A field programmable gate array (FPGA) within a processor receives the memory addresses of the network packets and retrieves the network packets. The network packets are analyzed by comparing at least one threat signature that is associated with undesired network behavior with the contents of the network packets. In response to the at least one threat signature matching the contents of at least one of the network packets, an intrusion alert is transmitted to the BMC.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 13, 2017
    Applicant: DELL PRODUCTS, L.P.
    Inventors: ELIE ANTOUN JREIJ, CHITRAK GUPTA, WADE ANDREW BUTCHER, SUSHMA BASAVARAJAIAH, RAMA RAO BISA
  • Patent number: 9619239
    Abstract: In accordance with embodiments of the present disclosure, a device for persistent cached image download may include a memory, an input/output interface, and a network interface. The memory may be configured to store therein an image database, the image database comprising a boot image for each of one or more information handling systems. The input/output interface may be communicatively coupled to the memory and configured to couple to a corresponding input/output port of an information handling system. The network interface may be configured to couple to an image server. In response to an information handling system coupled to the input/output interface determining that the updated version of the particular boot image exists at the image server, the memory may store the updated version in the memory as the particular boot image.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: April 11, 2017
    Assignee: Dell Products L.P.
    Inventors: Jonathan Foster Lewis, Wade Andrew Butcher, William A. Moyes, Philip John Brisky