Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.

Abstract: In a first aspect, a first method of determining radiation intensity is provided. The first method includes the steps of (1) providing a semiconductor device having (a) a silicon mesa; and (b) photo-gate conductor material along at least three sidewalls of the silicon mesa; (2) forming a depletion region in the silicon mesa; and (3) in response to radiation impacting the semiconductor device, creating a signal in the semiconductor device, wherein the signal has a level related to an intensity of the radiation. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.

Abstract: A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

Abstract: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI.

Abstract: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

Abstract: A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

Abstract: A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing an insulator over the conformal conductive liner; forming a contact pattern through the conformal conductive liner, the insulator and the first inter-level dielectric (ILD) layer; depositing a second conformal conductive liner over the MIMCAP pattern, the contact pattern and the first ILD layer; and depositing a conductive stud over the second conformal conductive liner in the MIMCAP pattern and the contact pattern. The method is applicable to both a conventional bulk semiconductor substrate and a silicon-on-insulator (SOI) substrate.

Abstract: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

Abstract: Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

Abstract: A cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.

Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

Abstract: The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

Abstract: The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

Abstract: A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).

Abstract: An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

Abstract: A precision voltage reference for ultra-thin gate oxide process technologies is realized with a network of tunneling current circuit elements. A voltage difference is measured between selected nodes of one or more current paths of a voltage divider. The tunneling current circuit element may be implemented with any suitable device, such as a parallel plate capacitor or MOSFET. The physical properties of gate tunneling currents enable the voltage reference output to be largely independent of temperature. The circuit may be implemented for low voltage operations with input power supply values of 1.2 volts or less. The output voltage tolerance may be designed to be about ±25% or less of a power supply voltage tolerance. In addition, variations in gate oxide thickness account for a change of less than about ±2% in the voltage reference generator output.