Patents by Inventor Wagdi Abadeer
Wagdi Abadeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060171189Abstract: An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.Type: ApplicationFiled: February 1, 2005Publication date: August 3, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, John Fifield, Harold Pilo
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Publication number: 20060091951Abstract: An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, Anthony Bonaccio, Kiran Chatty, John Fifield
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Publication number: 20060060938Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.Type: ApplicationFiled: September 23, 2004Publication date: March 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, John Fifield, Robert Gauthier, William Tonti
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Publication number: 20050189615Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.Type: ApplicationFiled: May 13, 2005Publication date: September 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, Eric Adler, Zhong-Xiang He, Bradley Orner, Vidhya Ramachandran, Barbara Waterhouse, Michael Zierak
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Publication number: 20050186744Abstract: An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.Type: ApplicationFiled: February 24, 2004Publication date: August 25, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, Jeffrey Brown, Kiran Chatty, Robert Gauthier,, Carl Radens, William Tonti
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Publication number: 20050133884Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).Type: ApplicationFiled: February 4, 2005Publication date: June 23, 2005Applicant: International Business Machines CorporationInventors: John Fifield, Wagdi Abadeer, William Tonti
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Publication number: 20050122160Abstract: A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.Type: ApplicationFiled: December 9, 2003Publication date: June 9, 2005Applicant: International Business Machines CorporationInventors: Wagdi Abadeer, Jennifer Appleyard, John Fifield, William Tonti
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Publication number: 20050090049Abstract: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI.Type: ApplicationFiled: November 18, 2004Publication date: April 28, 2005Inventors: Wagdi Abadeer, Jeffrey Brown, Robert Gauthier, Jed Rankin, William Tonti
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Publication number: 20050073354Abstract: A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).Type: ApplicationFiled: October 1, 2003Publication date: April 7, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, John Fifield, William Tonti
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Publication number: 20050073023Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).Type: ApplicationFiled: October 6, 2003Publication date: April 7, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Fifield, Wagdi Abadeer, William Tonti
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Patent number: 6714113Abstract: An inductor is integrated in VLSI and ULSI technology products for very high frequency applications. The inductor is in a microstrip transmission line configuration which can be designed in a form of straight line, spiral line or Meander line. The inductor is formed by shorting the microstrip center conductor to the lower level ground plane at one end of the transmission line. This results in an inductance which, for a given design of transmission line, and in a specified frequency range, is independent of frequency, within the operating design range. The microstrip transmission line provides an inductance which could be used on any type of substrate, with either low or high resistivity. The microstrip transmission line could utilize two or all of the metal wiring levels of the technology, allowing a wide range of inductance and quality factor design tradeoffs.Type: GrantFiled: November 14, 2000Date of Patent: March 30, 2004Assignee: International Business Machines CorporationInventors: Wagdi Abadeer, Robert A. Groves, Patrick Hansen