Patents by Inventor Wagdi W. Abadeer

Wagdi W. Abadeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263517
    Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES. INC.
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 8349697
    Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, William R. Tonti, Yun Shi
  • Publication number: 20120280356
    Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
    Type: Application
    Filed: July 19, 2012
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William Tonti
  • Publication number: 20120264275
    Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, William R. Tonti, Yun Shi
  • Patent number: 8216909
    Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, William R. Tonti, Yun Shi
  • Publication number: 20120128033
    Abstract: A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Cathryn J. Christiansen, John A. Fifield, Dimitris P. Ioannou, Tom C. Lee, Lilian Kamal
  • Publication number: 20120098087
    Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
    Type: Application
    Filed: January 3, 2012
    Publication date: April 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Publication number: 20120084741
    Abstract: A method of increasing an initial threshold voltage (Vt) of selected devices. The method includes designing devices with desired antenna effects and adjusting an increase in Vt of some devices to specific values. The desired antenna effects produce a desired threshold voltage of the devices.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. ABADEER, Lilian Kamal
  • Patent number: 8110483
    Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Jr., Robert R. Robison, William R. Tonti
  • Patent number: 8035452
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, John A. Fifield, Stephen D. Wyatt
  • Patent number: 8021950
    Abstract: Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, John J. Ellis-Monaghan, Jeffrey P. Gambino, Tom C. Lee
  • Patent number: 7977201
    Abstract: In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Robert Robison, Yun Shi, William R. Tonti
  • Publication number: 20110161896
    Abstract: In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert Robison, Yun Shi, William R. Tonti
  • Patent number: 7939911
    Abstract: In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Robert Robison, Yun Shi, William R. Tonti
  • Patent number: 7939395
    Abstract: Structures and methods for integrating a thick oxide high-voltage metal-oxide-semiconductor (MOS) device into a thin oxide silicon-on-insulator (SOI). A method of forming a semiconductor structure includes forming first source and drain regions of a first device below a buried oxide layer of a silicon-on-insulator (SOI) wafer, forming a gate of the first device in a layer of semiconductor material above the buried oxide layer; and forming second source and drain regions of a second device in the layer of semiconductor material above the buried oxide layer.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lillian Kamal, legal representative, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, Yun Shi, William R. Tonti
  • Publication number: 20110095366
    Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 7932552
    Abstract: Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Anthony R. Bonaccio, Joseph A. Iadanza
  • Publication number: 20110073985
    Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Applicant: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William Tonti
  • Patent number: 7916531
    Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Anthony R Bonaccio, Jack A Mandelman, William R. Tonti, Sebastian T Ventrone
  • Patent number: 7915571
    Abstract: Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, James W. Adkisson, Jeffrey S. Brown, Kiran V. Chatty, Robert J. Gauthier, Jr., Michael J. Hauser, Jed H. Rankin, William R. Tonti