BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES
In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
Latest IBM Patents:
This application is a divisional of U.S. patent application Ser. No. 12/191,683, filed Aug. 14, 2008, which is also related to co-pending U.S. patent application Ser. No. 12/191,633 filed Aug. 14, 2008, the entire contents and disclosures of which are incorporated herein by reference.
BACKGROUND OF THE INVENTIONThe present invention relates to semiconductor structures, and particularly to a back-end-of-line (BEOL) resistive structure comprising a doped semiconductor material, and design structures for the same.
Doped semiconductor materials are employed to form high resistivity elements in semiconductor devices such as a resistor or an electrical fuse. A resistor is a resistive circuit element that maintains a constant resistance value, and may be used in an RC circuit or any other circuit that requires an element with a constant resistance. An electrical fuse is a resistive circuit element that may change the value of the resistance upon programming. For example, when high electrical current flows through an electrical fuse, the material of the electrical fuse may be electromigrated or ruptured, thereby raising the resistance of the electrical fuse typically at least by an order of magnitude.
In the prior art, resistors and electrical fuses employing a doped semiconductor material are typically formed within a semiconductor substrate, i.e., below a top surface of a single crystalline semiconductor substrate, or at a gate level, i.e., at the same level as gate conductor lines. In the case of resistors and electrical fuses formed in the semiconductor substrate, dopants are introduced into portions of the semiconductor substrate to lower the resistivity of the semiconductor substrate sufficiently so that the doped semiconductor material has a reduced level of resistivity. In the case of resistors and electrical fuss formed at gate level, a doped polycrystalline semiconductor layer is formed directly on a gate dielectric layer by deposition of a doped semiconductor material or by deposition of an undoped semiconductor material. The doped semiconductor layer is lithographically patterned to form resistors and electrical fuses.
The doped semiconductor material has a higher resistivity than metallic materials, typically by at least two orders of magnitude. In the case of doped silicon, resistors and electrical fuses having a resistivity in the range from about 1.0×10−4 Ohm-cm to about 1.0 Ohm-cm may be formed by employing in-situ doping and/or ion implantation.
Such prior art doped semiconductor material form resistive structures located in the semiconductor substrate or directly on a gate dielectric below the first line level metal wiring structures, i.e., the level of metal lines that are closest to the semiconductor substrate. For this reason, the prior art resistive structures formed in the substrate or directly on a gate dielectric are “front-end-of-line” (FEOL) semiconductor structures located below the level of the first line level metal wiring structures and formed prior to formation of the first line level metal wiring structures. Each such FEOL resistive structure occupies an area of a semiconductor substrate that no other FEOL semiconductor device may occupy. Thus, formation of a FEOL resistive structure according to the prior art reduces area for other semiconductor devices, thereby limiting device density for FEOL semiconductor devices.
Further, the height or depth of the prior art FEOL resistive devices is limited either by the thickness of the gate conductor layer and the energy distribution of ion implantation. In addition, the width of the prior art FEOL resistive devices are limited by lithographic constraints since lithographic patterning determines the width of the prior art FEOL resistive devices. Thus, formation of a relatively high resistance structure requires a large structure located in or directly on the semiconductor substrate.
In view of the above, there exists a need for a resistive structure that occupies as small space as possible in front-end-of-line (FEOL) device areas, i.e., the volume beneath a first level metal wiring structures, and design structures for the same.
Further, there exists a need for a resistive structure that may provide a high resistance value with a minimal device volume, and particularly a resistive structure that may have a sublithographic width, and design structures for the same.
BRIEF SUMMARY OF THE INVENTIONThe present invention provides a semiconductor structure including a resistive structure comprising a doped semiconductor material and formed in back-end-of-line (BEOL), i.e., at or above a first line level metal wiring structure, and design structures for the same.
In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and at least partially overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. To form the BEOL resistive structure, a portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. A doped semiconductor plug may be formed instead of the doped semiconductor spacer. The resistive structure is located in a back-end-of-line structure, and therefore, does not occupy any space in front-end-of-line areas.
In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines. To form the BEOL resistive structure, an area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines. The dielectric layer may be a layer in BEOL, in which case the resistive structure does not occupy any space in front-end-of-line (FEOL) areas.
According to an aspect of the present invention, a semiconductor structure is provided, which comprises:
a first interconnect level structure including a first dielectric layer and a first metal line embedded therein;
a second interconnect level structure vertically abutting the first interconnect level structure and including a second dielectric layer and at least one second metal line embedded therein; and
a doped semiconductor structure laterally abutting the at least one second metal line and vertically abutting the first metal line.
In one embodiment, the doped semiconductor structure is a doped semiconductor spacer having a pair of substantially parallel sidewalls that directly adjoin the first metal line.
In another embodiment, the doped semiconductor spacer is topologically homeomorphic to a torus.
In even another embodiment, the semiconductor structure further comprises a third interconnect level structure vertically abutting the second interconnect level structure and including an upper portion of a third dielectric layer, wherein a lower portion of the third dielectric layer vertically abuts the first metal line.
In yet another embodiment, the semiconductor structure further comprises:
at least one additional metal line embedded in the second dielectric layer;
at least one interconnect via embedded in the second dielectric layer and vertically abutting the at least another second metal line; and
at least another first metal line embedded in the first dielectric layer and vertically abutting the at least one interconnect via.
In still another embodiment, the second interconnect level structure is completely filled with the second dielectric layer, the at least one second metal line, the doped semiconductor spacer, the lower portion of the third dielectric layer, the at least one additional metal line, and the at least one interconnect via.
In a further embodiment, the doped semiconductor structure comprises a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of the at least one second metal line.
In an even further embodiment, the semiconductor structure further comprises a third interconnect level structure vertically abutting the second interconnect level structure and including a third dielectric layer, wherein a top surface of the at least one second metal line, a top surface of the doped semiconductor plug, and a top surface of the second dielectric layer vertically abut a bottom surface of the third dielectric layer.
In a yet further embodiment, the semiconductor structure further comprises:
at least another second metal line embedded in the second dielectric layer;
at least one interconnect via embedded in the second dielectric layer and vertically abutting the at least another second metal line; and
at least another first metal line embedded in the first dielectric layer and vertically abutting the at least one interconnect via.
In a still further embodiment, the second interconnect level structure is completely filled with the second dielectric layer, the at least one second metal line, the doped semiconductor plug, the at least another second metal line, and the at least one interconnect via.
In further another embodiment, the doped semiconductor structure is polycrystalline and comprises one of silicon, a silicon germanium alloy portion, silicon, germanium, a silicon-germanium alloy portion, a silicon carbon alloy portion, a silicon-germanium-carbon alloy portion, gallium arsenide, indium arsenide, indium gallium arsenide, indium phosphide, lead sulfide, other III-V compound semiconductor materials, and II-VI compound semiconductor materials.
In an even further another embodiment, the semiconductor structure further comprises:
a semiconductor substrate located underneath the first interconnect level structure; and
at least one semiconductor device located directly on the semiconductor substrate and underneath the first interconnect level structure.
According to another aspect of the present invention, another semiconductor structure is provided, which comprises:
an interconnect level structure including a dielectric layer and first and second metal lines embedded therein; and
a doped semiconductor structure laterally abutting the first metal line and the second metal line.
In one embodiment, the doped semiconductor structure is a doped semiconductor spacer that is topologically homeomorphic to a torus.
In another embodiment, the semiconductor structure further comprises another interconnect level structure vertically abutting the interconnect level structure and including an upper portion of a another dielectric layer, wherein a lower portion of the other dielectric layer laterally abuts the doped semiconductor spacer.
In even another embodiment, the semiconductor structure further comprises:
at least one additional metal line embedded in the dielectric layer; and
at least one interconnect via embedded in the second dielectric layer and vertically abutting the at least another second metal line.
In yet another embodiment, the interconnect level structure is completely filled with the dielectric layer, the first metal line, the second metal line, the doped semiconductor spacer, the lower portion of the other dielectric layer, the at least one additional metal line, and the at least one interconnect via.
In still another embodiment, the doped semiconductor structure comprises a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of the first metal line and the second metal line.
In a further embodiment, the semiconductor structure further comprises:
a semiconductor substrate located underneath the first interconnect level structure; and
at least one semiconductor device located directly on the semiconductor substrate and underneath the first interconnect level structure.
According to yet another aspect of the present invention, a design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure is provided. The design structure comprises:
a first data representing a first interconnect level structure and including a second data representing a first dielectric layer and a third data representing a first metal line embedded in the first dielectric layer;
a fourth data representing a second interconnect level structure vertically abutting the first interconnect level structure and including a fifth data representing a second dielectric layer and a sixth data representing at least one second metal line embedded in the second dielectric layer; and
a seventh data representing a doped semiconductor structure laterally abutting the at least one second metal line and vertically abutting the first metal line.
In one embodiment, the seventh data represents a doped semiconductor spacer having a pair of substantially parallel sidewalls that directly adjoin the first metal line.
In another embodiment, the design structure further comprises:
an eighth data representing at least one additional metal line embedded in the second dielectric layer;
a ninth data representing at least one interconnect via embedded in the second dielectric layer and vertically abutting the at least another second metal line; and
a tenth data representing at least another first metal line embedded in the first dielectric layer and vertically abutting the at least one interconnect via.
In even another embodiment, the seventh data represents a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of the at least one second metal line.
In yet another embodiment, the design structure further comprises
an additional data representing a semiconductor substrate located underneath the interconnect level structure; and
another additional data representing at least one semiconductor device located directly on the semiconductor substrate and underneath the first interconnect level structure.
According to still another aspect of the present invention, another design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure is provided. The design structure comprises:
a first data representing an interconnect level structure and including a second data representing a dielectric layer, a third data representing a first metal line embedded in the dielectric layer, and a fourth data representing a second metal lines embedded in the dielectric layer; and
a fifth data representing a doped semiconductor structure laterally abutting the first metal line and the second metal line.
In one embodiment, the fifth data represents a doped semiconductor spacer that is topologically homeomorphic to a torus or a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of the first metal line and the second metal line.
In another embodiment, the design structure further comprises:
an additional data representing at least one additional metal line embedded in the dielectric layer; and
another additional data representing at least one interconnect via embedded in the second dielectric layer and vertically abutting the at least another second metal line.
In yet another embodiment, the fifth data represents a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of the first metal line and the second metal line.
In still another embodiment, the design structure further comprising a sixth data representing a semiconductor substrate located underneath the interconnect level structure; and
a seventh data representing at least one semiconductor device located directly on the semiconductor substrate and underneath the first interconnect level structure.
In all of the drawings herein, figures with the same numeric label and different alphabetical suffixes correspond to the same stage of a manufacturing process. Figures with the suffix “A” are top-down views. Figures with the suffix “B” or “C” are vertical cross-sectional views along the plane B-B′ or C-C′, respectively, of the corresponding figure with the same numeric label and the suffix “A.”
As stated above, the present invention relates to a back-end-of-line (BEOL) resistive structure comprising a doped semiconductor material, and design structures for the same, which are described herein with accompanying figures. As used herein, when introducing elements of the present invention or the preferred embodiments thereof, the articles “a”, “an”, “the” and “said” are intended to mean that there are one or more of the elements. Throughout the drawings, the same reference numerals or letters are used to designate like or equivalent elements. Detailed descriptions of known functions and constructions unnecessarily obscuring the subject matter of the present invention have been omitted for clarity. The drawings are not necessarily drawn to scale.
As used herein, a structural element is referred to as being “on” another structural element when the structural element is located directly on the other structural element or when a set of at least one intervening element making direct physical contact with the structural element and the other structural element is present. A structural element is referred to as being “directly on” another structural element when there is no intervening structural element and a physical contact is formed between the structural element and the other structural element. Likewise, an element is referred to as being “connected” or “coupled” to another element when the element is directly connected or coupled to the other element or when a set of at least one intervening element provides connection or coupling with the element and the other element. An element is referred to as being “directly connected” or “directly coupled” to another element when there is no intervening element and the connection or coupling is provided between the element and the other element. An element “abuts” another element when a physical interface area providing a direct contact is present between the element and the other element.
Referring to
The first interconnect level structure 11 may be formed on a substrate (not shown) such as a semiconductor substrate. As such, the first interconnect level structure 11 and the second interconnect level structure 31 may be a back-end-of-line (BEOL) metal interconnect structure that provides electrical wiring of semiconductor devices that are formed in, or directly on, the semiconductor substrate and known in the art as front-end-of-line (FEOL) semiconductor devices. The FEOL semiconductor devices are located below the level of first line level metal wiring structures, which are the line level metal wiring structures located closest to the semiconductor substrate among the line level metal wiring structures on the structure. The first line level is typically referred to as an “M1” level. As BEOL metal interconnect structures, the first interconnect level structure 11 is located at, or above, the level of the first line level metal wiring structures. The second interconnect level structure 31 is located above the level of the first line level metal wiring structures.
The first dielectric layer 10 and the second dielectric layer 30 comprise a dielectric material that are employed in BEOL interconnect structures. The dielectric materials that may be used for the first dielectric layer 10 and/or the second dielectric layer 30 include, but are not limited to, a silicate glass, an organosilicate glass (OSG) material, a SiCOH-based low-k material formed by chemical vapor deposition, a spin-on glass (SOG), or a spin-on low-k dielectric material such as SiLK™, etc. The silicate glass includes an undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), etc. The dielectric material may be a low dielectric constant (low-k) material having a dielectric constant less than 3.0. The dielectric material may non-porous or porous.
The dielectric material of the first dielectric layer 10 and the second dielectric layer 30 may be formed by plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, thermal chemical vapor deposition, spin coat and cure, etc. The thickness of each of the first dielectric layer 10 and the second dielectric layer 30 may be from about 100 nm to about 2,000 nm, and typically from about 200 nm to about 1,000 nm, although lesser and greater thicknesses are also contemplated herein.
The first metal line 20 and the at least one second metal line 40 are formed by etching line trenches in the first dielectric layer 10 and the second dielectric layer 30, respectively, and subsequently filling the line trenches with metal. The metal may be deposited into the line trenches, for example, by physical vapor deposition (sputtering), electroplating, electroless plating, chemical vapor deposition, or a combination thereof. Any portion of the metal overlying the top surfaces of the first dielectric layer 10 or the second dielectric layer 30 is removed, for example, by chemical mechanical polishing (CMP), recess etch, or a combination thereof. Additional metal lines (not shown) may be formed at the same level as the first metal line 20 and/or the at least one second metal line 40 to provide horizontal electrical wiring within the same line level. Additional conductive vias (not shown) may be formed underneath the first metal line 20 and/or the at least one second metal line 40 to provide vertical electrical connection between metal lines located at different levels. The thickness of each of the first metal line 20 and the at least one second metal line 40 may be from about 50 nm to about 1,000 nm, and typically from about 100 nm to about 500 nm, although lesser and greater thicknesses are also contemplated herein.
The at least one second metal line 40 at least partially overlie the first metal line 20. In other words, at least a portion of the area of the at least one second metal line 40 as seen in a top-down view such as the view of
Referring to
Employing the photoresist 47 and the at least one second metal line 40 as an etch mask, an etch is performed to recess the second dielectric layer 30 within the opening of the photoresist 47. The etch may be an anisotropic etch such as a reactive ion etch or an isotropic etch such as a wet etch. The expose portion of the second dielectric layer 30 is etched within the opening in the photoresist 47 selective to the at least one second metal line 40. A cavity 69 having an opening at the level of the top surface of the second interconnect level structure 31 is formed in the volume of the removed portion of the second dielectric layer 30 within the second interconnect level structure 31. Sidewalls of the at least one second metal line 40, sidewalls of the second dielectric layer 30, and a top surface of the first metal line 20 are exposed after the etch within the cavity 69.
In case the etch is an anisotropic etch, the sidewalls of the cavity 69 are substantially vertical, and may be substantially vertically coincident with the exposed sidewalls of the at least one second metal line 40 and the edges of the opening in the photoresist 47. Since the exposed portion of the at least one second metal line 40 within the opening protects the material of the second dielectric layer 30 directly underneath from the anisotropic etch, at least one portion of the second dielectric layer 30 which underlies a portion of the at least one second metal line 40 within the opening is formed after the first metal line 20 is exposed in the cavity 69. The cavity 69 extends from the top surface of the second interconnect level structure 31 to the bottom surface of the second interconnect level structure 31, which coincides with the top surface of the first interconnect level structure 11.
The photoresist 47 is subsequently removed. The exposed surfaces of the at least one second metal line 40, the first metal line 20, and the second dielectric layer 30 may be cleaned to remove residual polymers from the etch, if any.
Referring to
Non-limiting examples of semiconductor materials that may be employed for the semiconductor layer 50L include silicon, a silicon germanium alloy portion, silicon, germanium, a silicon-germanium alloy portion, a silicon carbon alloy portion, a silicon-germanium-carbon alloy portion, gallium arsenide, indium arsenide, indium gallium arsenide, indium phosphide, lead sulfide, other III-V compound semiconductor materials, and II-VI compound semiconductor materials. A common semiconductor material for the semiconductor layer 50L is polysilicon, i.e., silicon in polycrystalline form. The semiconductor layer 50L may be formed by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), thermal chemical vapor deposition, etc. The semiconductor layer 50L may be conformal or non-conformal.
The semiconductor layer 50L is doped with electrical dopants, i.e., dopants that provide charge carriers in the semiconductor layer 50L to increase the conductivity of the semiconductor layer 50L above the level of conductivity of an intrinsic semiconductor material, which is typically too low and difficult to control for resistive structures with a controlled resistance. For example, the semiconductor layer 50L may comprise doped polysilicon, a doped silicon-containing alloy, a doped germanium-containing alloy, a doped compound semiconductor material, etc. The electrical dopants may be p-type dopants such as B, Ga, and/or In, or n-type dopants such as P, As, and/or Sb. The dopants may be introduced into the semiconductor layer 50L by in-situ doping, i.e., incorporation of dopants from a gas stream into the deposited semiconductor material of the semiconductor layer 50L while the deposition is in progress in a reactor, or may be introduced into the semiconductor layer 50L by ion implantation. In case the semiconductor layer 50L comprises silicon, a resistivity range from about 1.0×10−4 Ohm-cm to about 1.0 Ohm-cm may be achieved by ion implantation, although higher resistivity ranges are also contemplated herein. The dopant concentration in the semiconductor layer 50L may be optimized for the desired resistance value of a doped semiconductor structure to be subsequently formed from a portion of the semiconductor layer 50L.
The thickness of the semiconductor layer 50L is set such that the cavity 69 is not completely filled with the semiconductor layer 50L. The thickness of the semiconductor layer 50L may be from about 15 nm to about 500 nm, and typically from about 30 nm to about 150 nm, although lesser and greater thicknesses are also contemplated herein. The thickness of the semiconductor layer 50L may also be optimized for the desired resistance value of the doped semiconductor structure to be subsequently formed.
Referring to
The doped semiconductor spacer 50 is a doped semiconductor structure comprising a doped semiconductor material. The doped semiconductor spacer 50 comprises a doped polycrystalline semiconductor material of the semiconductor layer 50L. The doped semiconductor spacer 50 laterally surrounds the cavity 69. A top surface of the first metal line 20 is exposed underneath the cavity 69. The doped semiconductor spacer 50 laterally abuts the sidewalls of the at least one second metal line 40 and vertically abuts the top surface of the first metal line 20. The doped semiconductor spacer 50 has at least one pair of substantially parallel sidewalls that directly adjoin the first metal line 20.
Since the doped semiconductor spacer 50L is formed on the sidewalls of the at least one second metal line 40 and the second dielectric layer 30 that surround the cavity 69, the doped semiconductor spacer 50 may be ring-shaped, or “topologically homeomorphic to a torus.” Homeomorphism in topology refers to a continuous stretching and bending of the object into a new shape. Continuous stretching involves a transformation without formation of any mathematical singularity, i.e., without removing any existing hole or forming a new hole in the shape. A torus has one topological handle, or a topological object of “genus 1.” The doped semiconductor spacer 50L laterally surrounds the cavity 69, but does not fill the cavity 69, and has no twisted features. Therefore, the doped semiconductor spacer 50L may be continuously transformed into a torus by stretching and bending, and is therefore topologically homeomorphic to a torus.
Referring to
The upper portion of the third dielectric layer 70, which is located above the top surface of the at least one second metal line 40 and top surface of the second dielectric layer 30, is formed in the same deposition step as the lower portion of the third dielectric layer 70. The upper portion of the third dielectric layer 70 and the lower portion of the third dielectric layer 70 comprise the same dielectric material and are of integral construction without any physically manifested interface therebetween.
At least one third metal line 80 and at least one conductive via (not shown) may be formed in the upper portion of the third dielectric layer 70. The upper portion of the third dielectric layer 70 above the top surface of the second interconnect level structure 31, the at least one third metal line 80, and the at least one conductive via embedded in the upper portion of the third dielectric layer 70 collectively constitute a third interconnect level structure 71. The third interconnect level structure 71 is located directly on, and above the top surface of, the second interconnect level structure 31.
Referring to
Referring to
In one case, the second interconnect level structure 31 may be completely filled with the second dielectric layer 30, the at least one second metal line 40, the doped semiconductor spacer 50, the lower portion of the third dielectric layer 70, the at least one additional metal line 40′, and the at least one interconnect via 38.
The first exemplary semiconductor structure further comprises a semiconductor substrate 208 and a first BEOL level structure 250 located underneath the first exemplary BEOL semiconductor structure 100. The first BEOL level structure 250 includes first line level metal wiring structures such as at least one first-level metal line 240. In one case, the first exemplary BEOL semiconductor structure 100 may vertically abut the first BEOL level structure 250. In another case, at least one intervening interconnect level structure (not shown) may be formed between the first exemplary BEOL semiconductor structure 100 and the first BEOL level structure 250. In yet another case, the first interconnect level structure 11 may be at the same level as, and overlap with, the first BEOL level structure 250. In other words, the first metal line 20 may be one of the first line level metal wiring structures and located at the same level as the at least one first-level metal line 240, and the first interconnect level structure 11 and the first BEOL level structure 250 are one and the same.
The semiconductor substrate 208 comprises a semiconductor layer 210 and at least one semiconductor device formed in the semiconductor substrate 208 or directly on the semiconductor substrate 208. For example, the semiconductor substrate 208 may include at least one shallow trench isolation structure 218 that provides electrical isolation between adjacent semiconductor devices. The at least one semiconductor device may include, for example, a field effect transistor having a gate dielectric 220, a gate electrode 222, and a gate spacer formed on the surface of the semiconductor layer 210 and source and drain regions 212 formed within the semiconductor substrate 208. The at least one semiconductor device may be electrically connected to the metal interconnect structures above through at least one contact level via 238 and the at least one first-level metal line 240, which are embedded in a first BEOL level dielectric layer 230 that vertically abut the semiconductor substrate 208.
The doped semiconductor spacer 50 functions as a resistive link for a resistor or an electrical fuse. If the doped semiconductor spacer 50 is employed for a resistor, the current density through the doped semiconductor spacer 50 is maintained below a predetermined level to prevent change in resistance due to structural changes. If the doped semiconductor spacer 50 is employed for an electrical fuse, the doped semiconductor spacer may be “programmed” to change the resistance, typically by increasing the resistance, by passing enough current to cause structural changes and accompanying increase in resistance. Since the doped semiconductor spacer 50 is formed within an interconnect level structure, and not in the semiconductor substrate 208 or on the surface of the semiconductor layer 210, the doped semiconductor spacer 50 is not a FEOL device and does not occupy any volume in or directly on the semiconductor substrate 208. Thus, more other FEOL devices may be formed on the semiconductor substrate 208 by forming the doped semiconductor structure 50 as a resistive device element in the BEOL, thereby enabling higher density semiconductor structures.
Referring to
After removing the photoresist 47 (See
The thickness of the semiconductor layer 50L is set such that the cavity 69 is completely filled with the semiconductor layer 50L. The thickness of the semiconductor layer 50L may be from about 50 nm to about 2,000 nm, and typically from about 100 nm to about 1,000 nm, although lesser and greater thicknesses are also contemplated herein.
Referring to
The doped semiconductor plug 52 is a doped semiconductor structure comprising a doped semiconductor material. The doped semiconductor plug 52 comprises a doped polycrystalline semiconductor material of the semiconductor layer 50L. The doped semiconductor plug 52 completely fills the cavity 69 (See
Referring to
At least one third metal line 80 and at least one conductive via (not shown) may be formed in the third dielectric layer 70. The third dielectric layer 70 above the top surface of the second interconnect level structure 31, the at least one third metal line 80, and the at least one conductive via embedded in the upper portion of the third dielectric layer 70 collectively constitute a third interconnect level structure 71. The third interconnect level structure 71 is located directly on, and above the top surface of, the second interconnect level structure 31.
Referring to
In one case, the second interconnect level structure 31 may be completely filled with the second dielectric layer 30, the at least one second metal line 40, the doped semiconductor plug 52, the at least one additional metal line 40′, and the at least one interconnect via 38.
The second exemplary semiconductor structure further comprises a semiconductor substrate 208 and a first BEOL level structure 250 located underneath the second exemplary BEOL semiconductor structure 100′. The doped semiconductor plug 52 functions as a resistive link for a resistor or an electrical fuse in the same manner as in the first embodiment of the present invention. Since the doped semiconductor plug 52 is formed within an interconnect level structure in BEOL, the doped semiconductor plug 52 does not occupy any space in or directly on the semiconductor substrate 208, thereby enabling formation of additional semiconductor devices directly on the semiconductor substrate 208.
Referring to
The underlying interconnect level structure 111 may be formed on a substrate (not shown) such as a semiconductor substrate. As such, the underlying interconnect level structure 111 and the interconnect level structure 131 may be a back-end-of-line (BEOL) metal interconnect structure that provides electrical wiring of semiconductor devices that are formed in or directly on the semiconductor substrate and known in the art as front-end-of-line (FEOL) semiconductor devices. The FEOL semiconductor devices are located below the level of first line level metal wiring structures, which are the line level metal wiring structures located closest to the semiconductor substrate among the line level metal wiring structures on the structure. As BEOL metal interconnect structures, the underlying interconnect level structure 111 is located at or above the level of the first line level metal wiring structures. The interconnect level structure 131 is located above the level of the first line level metal wiring structures.
The underlying dielectric layer 110 and the dielectric layer 130 comprises a dielectric material that are employed in BEOL interconnect structures. The underlying dielectric layer 110 and the dielectric layer 130 may have the same composition and thickness as, and may be formed employing the same methods as, the first, second, and third dielectric layers (10, 30, 70) in the first and second embodiment of the present invention described above.
A first metal line 142 and a second metal line 144 are formed by etching line trenches in the dielectric layer 130 and subsequently filling the line trenches with metal. The metal may be deposited into the line trenches, for example, by physical vapor deposition (sputtering), electroplating, electroless plating, chemical vapor deposition, or a combination thereof. Any portion of the metal overlying the top surfaces of the dielectric layer 130 is removed, for example, by chemical mechanical polishing (CMP), recess etch, or a combination thereof. Additional metal lines (not shown) may be formed at the same level as the first metal line 142 and the second metal line 144 to provide horizontal electrical wiring within the interconnect level structure 131. Additional conductive vias (not shown) may be formed underneath the first metal line 142 and/or the second metal line 144 within the interconnect level structure 131 to provide vertical electrical connection to metal lines (not shown) in the underlying interconnect level structure 111. The thickness of each of the first metal line 141 and the second metal line 144 may be from about 50 nm to about 1,000 nm, and typically from about 100 nm to about 500 nm, although lesser and greater thicknesses are also contemplated herein. The first metal line 142 and the second metal line 144 are separated by a portion of the dielectric layer 130.
Referring to
Employing the photoresist 147, the first metal line 142, and the second metal line 144 as an etch mask, an etch is performed to recess the dielectric layer 130 within the opening of the photoresist 147. The etch may be an anisotropic etch such as a reactive ion etch or an isotropic etch such as a wet etch. The expose portion of the dielectric layer 130 is etched within the opening in the photoresist 147 selective to the first metal line 142 and the second metal line 144. A cavity 169 having an opening at the level of the top surface of the interconnect level structure 131 is formed in the volume of the removed portion of the dielectric layer 130 within the interconnect level structure 131. The depth of the cavity 169, as measured from the top surfaces of the first and second metal lines (142, 144) to the bottom surface of the cavity 169, may be less than the thickness of the first and second metal lines (142, 144). Sidewalls of the first metal line 142, the second metal line 144, and the dielectric layer 130 are exposed after the etch within the cavity 169. The photoresist 147 is subsequently removed. The exposed surfaces of the first metal line 142, the second metal line 144, and the dielectric layer 130 may be cleaned to remove residual polymers from the etch, if any.
Referring to
The semiconductor layer 150L is doped with electrical dopants, i.e., dopants that provide charge carriers in the semiconductor layer 150L to increase the conductivity of the semiconductor layer 150L above the level of conductivity of an intrinsic semiconductor material, which is typically too low and difficult to control for resistive structures with a controlled resistance. The doping of the semiconductor layer 150L may employ the same methods as the doping of the semiconductor layer 50L of the first and second embodiments.
The thickness of the semiconductor layer 150L is set such that the cavity 169 is not completely filled with the semiconductor layer 150L. The thickness of the semiconductor layer 150L may be from about 15 nm to about 500 nm, and typically from about 30 nm to about 150 nm, although lesser and greater thicknesses are also contemplated herein. The thickness of the semiconductor layer 150L may also be optimized for the desired resistance value of a doped semiconductor structure to be subsequently formed.
Referring to
The doped semiconductor spacer 150 is a doped semiconductor structure comprising a doped semiconductor material. The doped semiconductor spacer 150 comprises a doped polycrystalline semiconductor material of the semiconductor layer 150L. The doped semiconductor spacer 150 laterally surrounds the cavity 169. A recessed surface of the dielectric layer 130 is exposed underneath the cavity 169. The doped semiconductor spacer 150 laterally abuts the sidewalls of the first metal line 142 and the second metal line 144. The doped semiconductor spacer 150 has at least one pair of substantially parallel sidewalls that directly adjoin the recessed surface of the dielectric layer 130 at the bottom of the cavity 169.
Since the doped semiconductor spacer 150L is formed on the sidewalls of the first metal line 142, the second metal line 144, and the dielectric layer 130 that surround the cavity 169, the doped semiconductor spacer 150 may be ring-shaped, or topologically homeomorphic to a torus in the same manner as the doped semiconductor 50 of the first embodiment of the present invention.
Referring to
The upper portion of the overlying dielectric layer 170, which is located above the top surface of the at least one second metal line 40 and top surface of the dielectric layer 130, is formed in the same deposition step as the lower portion of the overlying dielectric layer 170. The upper portion of the overlying dielectric layer 170 and the lower portion of the overlying dielectric layer 170 comprise the same dielectric material and are of integral construction without any physically manifested interface therebetween.
At least one third metal line 180 and at least one conductive via (not shown) may be formed in the upper portion of the overlying dielectric layer 170. The upper portion of the overlying dielectric layer 170 above the top surface of the interconnect level structure 131, the at least one third metal line 80, and the at least one conductive via embedded in the upper portion of the overlying dielectric layer 170 collectively constitute an overlying interconnect level structure 171. The overlying interconnect level structure 171 is located directly on, and above the top surface of, the interconnect level structure 131.
Referring to
In one case, the interconnect level structure 131 may be completely filled with the dielectric layer 130, the first metal line 142, the second metal line 144, the doped semiconductor spacer 150, the lower portion of the overlying dielectric layer 170, the at least one additional metal line 40′, and the at least one interconnect via 38.
The third exemplary semiconductor structure further comprises a semiconductor substrate 208 and a first BEOL level structure 250 located underneath the first exemplary BEOL semiconductor structure 200. The first BEOL level structure 250 and the semiconductor substrate 208 may be substantially the same as described in the first and second embodiments of the present invention.
The doped semiconductor spacer 150 functions as a resistive link for a resistor or an electrical fuse in the same manner as in the first and second embodiments. Since the doped semiconductor spacer 150 is formed within an interconnect level structure, and not in the semiconductor substrate 208 or on the surface of the semiconductor layer 210, the doped semiconductor spacer 150 is not a FEOL device and does not occupy any volume in or directly on the semiconductor substrate 208. Thus, more other FEOL devices may be formed on the semiconductor substrate 208 by forming the doped semiconductor structure 150 as a resistive device element in the BEOL, thereby enabling higher density semiconductor structures.
Referring to
After removing the photoresist 147 (See
An anisotropic etch is performed on the doped semiconductor layer to form a doped semiconductor spacer 150. The doped semiconductor spacer 150 is a doped semiconductor structure comprising a doped semiconductor material. The doped semiconductor spacer 150 comprises a doped polycrystalline semiconductor material of the semiconductor layer 150L. The doped semiconductor spacer 150 laterally surrounds the cavity 169. If the cavity extends to the bottom of the interconnect level structure 131, a top surface of the underlying interconnect level structure 111 such as the underlying dielectric layer 110 may be exposed underneath the cavity 169. If the bottom surface of the cavity 169 is located above the bottom surface of the interconnect level structure 131, a recessed surface of the dielectric layer 130 is exposed at the bottom of the cavity 169. The doped semiconductor spacer 150 laterally abuts the sidewalls of the first metal line 142 and the second metal line 144 to provide a resistive link therebetween.
Since the doped semiconductor spacer 150L is formed on the sidewalls of the first metal line 142, the second metal line 144, and the dielectric layer 130 that surround the cavity 169, the doped semiconductor spacer 150 may be ring-shaped, or topologically homeomorphic to a torus in the same manner as the doped semiconductor 50 of the first embodiment of the present invention.
Referring to
The upper portion of the overlying dielectric layer 170, which is located above the top surface of the at least one second metal line 40 and top surface of the dielectric layer 130, is formed in the same deposition step as the lower portion of the overlying dielectric layer 170. The upper portion of the overlying dielectric layer 170 and the lower portion of the overlying dielectric layer 170 comprise the same dielectric material and are of integral construction without any physically manifested interface therebetween.
At least one third metal line 180 and at least one conductive via (not shown) may be formed in the upper portion of the overlying dielectric layer 170. The upper portion of the overlying dielectric layer 170 above the top surface of the interconnect level structure 131, the at least one third metal line 80, and the at least one conductive via embedded in the upper portion of the overlying dielectric layer 170 collectively constitute an overlying interconnect level structure 171. The overlying interconnect level structure 171 is located directly on, and above the top surface of, the interconnect level structure 131.
Referring to
In one case, the interconnect level structure 131 may be completely filled with the dielectric layer 130, the first metal line 142, the second metal line 144, the doped semiconductor spacer 150, the lower portion of the overlying dielectric layer 170, the at least one additional metal line 40′, and the at least one interconnect via 38.
The fourth exemplary semiconductor structure further comprises a semiconductor substrate 208 and a first BEOL level structure 250 located underneath the fourth exemplary BEOL semiconductor structure 200′. The first BEOL level structure 250 and the semiconductor substrate 208 may be substantially the same as described in the first through third embodiments of the present invention. The doped semiconductor spacer 150 functions as a resistive link for a resistor or an electrical fuse in the same manner as in the third embodiment.
Referring to
A semiconductor layer (not shown) is formed on the top surface and sidewalls of the first metal line 142 and the second metal line 144 and the exposed surfaces of the dielectric layer 130 within the cavity 169. The semiconductor layer of the fifth embodiment comprises the same semiconductor material as the semiconductor layer 50L or the semiconductor layer 150L of the first through fourth embodiment. Particularly, the semiconductor layer is doped with electrical dopants to provide the same level of resistivity as in the first through fourth embodiments.
The thickness of the semiconductor layer is set such that the cavity 169 is completely filled with the semiconductor layer. The thickness of the semiconductor layer may be from about 50 nm to about 2,000 nm, and typically from about 100 nm to about 1,000 nm, although lesser and greater thicknesses are also contemplated herein.
The semiconductor layer is subsequently planarized to the level of the top surface of the interconnect level structure 131, i.e., the top surface of the first and second metal lines (142, 144). Chemical mechanical planarization (CMP), a recess etch, or a combination thereof may be employed to remove the excess material of the semiconductor layer from above the top surface of the interconnect level structure 131. The remaining vertical portion of the semiconductor layer located beneath the top surface of the interconnect level structure 131 constitutes a doped semiconductor plug 152.
The doped semiconductor plug 152 is a doped semiconductor structure comprising a doped semiconductor material. The doped semiconductor plug 152 comprises a doped polycrystalline semiconductor material of the semiconductor layer. The doped semiconductor plug 152 completely fills the cavity 169 (See
An overlying interconnect level structure 171 including an overlying third dielectric layer 170 is formed over the top surface of the interconnect level structure 131 in the same manner as in the third and fourth embodiment of the present invention.
Referring to
In one case, the interconnect level structure 131 may be completely filled with the dielectric layer 130, the first metal line 142, the second metal line 144, the doped semiconductor spacer 150, the lower portion of the overlying dielectric layer 170, the at least one additional metal line 40′, and the at least one interconnect via 38.
The fifth exemplary semiconductor structure further comprises a semiconductor substrate 208 and a first BEOL level structure 250 located underneath the fifth exemplary BEOL semiconductor structure 200″. The first BEOL level structure 250 and the semiconductor substrate 208 may be substantially the same as described in the first through fourth embodiments of the present invention. The doped semiconductor plug 152 functions as a resistive link for a resistor or an electrical fuse in the same manner as in the third and fourth embodiments.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990. Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the following claims.
Claims
1. A non-transitory machine readable medium embodying a design structure for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:
- a first data representing a first interconnect level structure and including a second data representing a first dielectric layer and a third data representing a first metal line embedded in said first dielectric layer;
- a fourth data representing a second interconnect level structure vertically abutting said first interconnect level structure and including a fifth data representing a second dielectric layer and a sixth data representing at least one second metal line embedded in said second dielectric layer; and
- a seventh data representing a doped semiconductor structure laterally abutting said at least one second metal line and vertically abutting said first metal line.
2. The non-transitory machine readable medium of claim 1, wherein said seventh data represents a doped semiconductor spacer having a pair of substantially parallel sidewalls that directly adjoin said first metal line.
3. The non-transitory machine readable medium of claim 1, wherein said design structure further comprises:
- an eighth data representing at least one additional metal line embedded in said second dielectric layer;
- a ninth data representing at least one interconnect via embedded in said second dielectric layer and vertically abutting said at least another second metal line; and
- a tenth data representing at least another first metal line embedded in said first dielectric layer and vertically abutting said at least one interconnect via.
4. The non-transitory machine readable medium of claim 1, wherein said seventh data represents a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of said at least one second metal line.
5. A non-transitory machine readable medium embodying a design structure for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:
- a first data representing an interconnect level structure and including a second data representing a dielectric layer, a third data representing a first metal line embedded in said dielectric layer, and a fourth data representing a second metal lines embedded in said dielectric layer; and
- a fifth data representing a doped semiconductor structure laterally abutting said first metal line and said second metal line.
6. The non-transitory machine readable medium of claim 5, wherein said fifth data represents a doped semiconductor spacer that is topologically homeomorphic to a torus or a doped semiconductor plug having a top surface that is substantially coplanar with a top surface of said first metal line and said second metal line.
7. The non-transitory machine readable medium of claim 5, wherein said design structure further comprises:
- a sixth data representing a semiconductor substrate located underneath said interconnect level structure; and
- a seventh data representing at least one semiconductor device located directly on said semiconductor substrate and underneath said first interconnect level structure.
Type: Application
Filed: Mar 8, 2011
Publication Date: Jun 30, 2011
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Wagdi W. Abadeer (Jericho, VT), Kiran V. Chatty (Williston, VT), Robert J. Gauthier, JR. (Hinesburg, VT), Jed H. Rankin (Richmon, VT), Robert Robison (Colchester, VT), Yun Shi (South Burlington, VT), William R. Tonti (Essex Junction, VT)
Application Number: 13/042,947
