Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

Abstract: Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications are disclosed. In exemplary aspects disclosed herein, MTJ devices are fabricated in a semiconductor die to provide at least two different memory arrays. MTJ devices in each memory array are fabricated to have different breakdown voltages. For example, it may be desired to fabricate a One-Time-Programmable (OTP) memory array in the semiconductor die using MTJ devices having a first, lower breakdown voltage, and a separate magneto-resistive random access memory (MRAM) in a same semiconductor die with MTJ devices having a higher breakdown voltage. Thus, in this example, lower breakdown voltage MTJ devices in OTP memory array require less voltage to program, while higher breakdown voltage MTJ devices in MRAM can maintain a desired write operation margin to avoid or reduce write operations causing dielectric breakdown.

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.

Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract: A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value.

Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

Abstract: A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value.

Abstract: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.

Abstract: Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage.