Patents by Inventor Wai Kei Mak

Wai Kei Mak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200380194
    Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Inventors: Meng-Kai HSU, Sheng-Hsiung CHEN, Wai-Kei MAK, Ting-Chi WANG, Yu-Hsiang CHENG, Ding-Wei HUANG
  • Patent number: 10776551
    Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Kai Hsu, Sheng-Hsiung Chen, Wai-Kei Mak, Ting-Chi Wang, Yu-Hsiang Cheng, Ding-Wei Huang
  • Publication number: 20200004912
    Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.
    Type: Application
    Filed: June 14, 2019
    Publication date: January 2, 2020
    Inventors: Meng-Kai HSU, Sheng-Hsiung CHEN, Wai-Kei MAK, Ting-Chi WANG, Yu-Hsiang CHENG, Ding-Wei HUANG
  • Patent number: 10474038
    Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
  • Publication number: 20190094709
    Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Inventors: BO-YANG CHEN, CHI-CHUN FANG, WAI-KEI MAK, TING-CHI WANG
  • Patent number: 10192019
    Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: January 29, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 9665679
    Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 30, 2017
    Assignee: Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20150089465
    Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20150007123
    Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ration for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8875081
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 28, 2014
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20140068542
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Application
    Filed: February 26, 2013
    Publication date: March 6, 2014
    Applicants: SpringSoft USA, Inc, SpringSoft, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8407647
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: March 26, 2013
    Assignees: Springsoft, Inc., Springsoft USA, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8336001
    Abstract: A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 18, 2012
    Assignee: Springsoft, Inc.
    Inventors: Fong-Yuan Chang, Wai-Kei Mak, Ren-Song Tsay
  • Publication number: 20110154282
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 23, 2011
    Inventors: Fong-Yuan CHANG, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20110107278
    Abstract: A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest
    Type: Application
    Filed: October 27, 2010
    Publication date: May 5, 2011
    Inventors: Fong-Yuan Chang, Wai-Kei Mak, Ren-Song Tsay
  • Patent number: 7917880
    Abstract: A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: March 29, 2011
    Assignee: National Tsing Hua University
    Inventors: Wai Kei Mak, Wei Chung Chao
  • Publication number: 20090228844
    Abstract: A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 10, 2009
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Wai Kei Mak, Wei Chung Chao