Abstract: A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.

Abstract: A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.