Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

Abstract: A transistor gate is disclosed. The transistor gate includes a first part above a substrate that has a first width and a second part above the first part that is centered with respect to the first part and that has a second width that is greater than the first width. The first part and the second part form a single monolithic T-gate structure.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.

Abstract: Embodiments described herein comprise a transistor device that comprises a GaN channel. In an embodiment, the transistor device further comprises a source region and a drain region. The source region may be separated from the drain region by the GaN channel. In an embodiment, the source region and the drain region comprise surfaces with a root mean squared (RMS) surface roughness greater than 3 nm. In an embodiment, the transistor device further comprises a gate electrode over the GaN channel, a source contact in contact with source region, and a drain contact in contact with the drain region.

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

Abstract: Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

Abstract: Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

Abstract: An antifuse may include a non-planar conductive terminal having a high-z portion extending to a greater z-height than a low-z portion. A second conductive terminal is disposed over the low-z portion and separated from the first terminal by at least one intervening dielectric material. Fabrication of an antifuse may include forming a first opening in a first dielectric material disposed over a substrate, and undercutting a region of the first dielectric material. The undercut region of the first dielectric material is lined with a second dielectric material, such as gate dielectric material, through the first opening. A conductive first terminal material backfills the lined undercut region through the first opening. A second opening through the first dielectric material exposes the second dielectric material lining the undercut region. A conductive second terminal material is backfilled in the second opening.

Abstract: Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

Abstract: A method for producing controllable light emission from a semiconductor device includes the following steps: providing a heterojunction bipolar transistor device that includes collector, base, and emitter regions; and applying electrical signals across terminals coupled with the collector, base, and emitter regions to cause light emission by radiative recombination in the base region. In a disclosed embodiment, the step of applying electrical signals includes applying a collector-to-emitter voltage and modulating light output by applying a modulating base current.