Patents by Inventor Walter James Scheuermann
Walter James Scheuermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8543794Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: GrantFiled: January 19, 2012Date of Patent: September 24, 2013Assignee: Altera CorporationInventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Patent number: 8533431Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: GrantFiled: October 15, 2008Date of Patent: September 10, 2013Assignee: Altera CorporationInventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Patent number: 8406281Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: GrantFiled: October 28, 2009Date of Patent: March 26, 2013Assignee: QST Holdings LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Patent number: 8356161Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: GrantFiled: October 15, 2008Date of Patent: January 15, 2013Assignee: QST Holdings LLCInventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20120265914Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: January 19, 2012Publication date: October 18, 2012Applicant: QST Holdings LLCInventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20120124333Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: January 19, 2012Publication date: May 17, 2012Applicant: QST Holdings LLCInventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Patent number: 8010593Abstract: The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: GrantFiled: December 17, 2007Date of Patent: August 30, 2011Assignee: QST Holdings LLCInventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Patent number: 7962716Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: GrantFiled: November 17, 2004Date of Patent: June 14, 2011Assignee: QST Holdings, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Patent number: 7873881Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.Type: GrantFiled: March 6, 2007Date of Patent: January 18, 2011Assignee: NVIDIA CorporationInventors: Brian Box, John M. Rudosky, Walter James Scheuermann
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Publication number: 20100220706Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: October 28, 2009Publication date: September 2, 2010Inventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20100161940Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: March 8, 2010Publication date: June 24, 2010Applicant: QST Holdings, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Patent number: 7620097Abstract: A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.Type: GrantFiled: December 23, 2008Date of Patent: November 17, 2009Assignee: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20090161863Abstract: An integrated circuit for implementing the secure hash algorithm is provided, According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller flirter includes an address control module and a finite state machine.Type: ApplicationFiled: January 14, 2009Publication date: June 25, 2009Applicant: QST HOLDINGS, LLCInventor: Walter James SCHEUERMANN
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Publication number: 20090103594Abstract: A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Publication number: 20090104930Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: QST Holdings, LLCInventors: Ghobad Heidari, Kuor-Hsin Chang, Paul L. Master, Eugene B. Hogenauer, Walter James Scheuermann
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Patent number: 7506237Abstract: A reconfigurable bit-manipulation node is disclosed that includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit is comprised of interconnected elements that include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.Type: GrantFiled: March 6, 2007Date of Patent: March 17, 2009Assignee: NVIDIA CorporationInventors: Brian Box, John M. Rudosky, Walter James Scheuermann
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Patent number: 7489779Abstract: An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.Type: GrantFiled: March 5, 2002Date of Patent: February 10, 2009Assignee: QSTHoldings, LLCInventor: Walter James Scheuermann
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Publication number: 20090037691Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: Quicksilver Technology, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20090037692Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: Quicksilver Technology, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann
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Publication number: 20090037693Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.Type: ApplicationFiled: October 15, 2008Publication date: February 5, 2009Applicant: Quicksilver Technology, Inc.Inventors: Paul L. Master, Eugene Hogenauer, Walter James Scheuermann