Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources.

Abstract: A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences-the number depending upon availability of the plurality of computational units from providing the other hardware resources.

Abstract: An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An interconnection network is coupled to a second group of computational elements to configures the second group for a second operation.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements includes a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up-table memory and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.