Patents by Inventor Walter R. Steiner

Walter R. Steiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10282803
    Abstract: One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 7, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad S. Hakura, Pierre Souillot, Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner
  • Patent number: 10032243
    Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed cache tiling. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: July 24, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad S. Hakura, Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner
  • Patent number: 9947084
    Abstract: A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes—a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 17, 2018
    Assignee: NVIDIA Corporation
    Inventors: Eric B. Lum, John S. Montrym, Walter R. Steiner, Justin Cobb, Henry Packard Moreton
  • Patent number: 9792122
    Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 17, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad S. Hakura, Walter R. Steiner, Cynthia Ann Edgeworth Allison, Rouslan Dimitrov, Karim M. Abdalla, Dale L. Kirkland, Emmett M. Kilgariff
  • Patent number: 9633458
    Abstract: In a graphics processing pipeline, a processing unit establishes a bounding box around a polygon in order to identify sample points that are covered by the polygon. For a given sample point included within the bounding box, the processing unit constructs a set of lines that intersect at the sample point, where each line in the set of lines is parallel to at least one side of the polygon. When all vertices of the polygon reside on one side of at least one line in the set of lines, the processing unit may reduce the size of the bounding box to exclude the sample point.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 25, 2017
    Assignee: NVIDIA Corporation
    Inventors: Walter R. Steiner, Eric Lum, Dale L. Kirkland, Steven James Heinrich, David Charles Patrick
  • Patent number: 9495781
    Abstract: A technique for early sample evaluation during coarse rasterization of primitives reduces the number of pixel tiles that are processed during fine rasterization of the primitive. A primitive bounding box determines when a primitive is small and may not actually cover any samples within at least one fine raster tile. Early sample evaluation is performed for the small primitive during coarse rasterization and the small primitive is discarded when no samples are actually covered by the small primitive. When the small primitive lies on a boundary between at least two fine raster tiles, early sample evaluation is performed during coarse rasterization to correctly identify which, if any, of the at least two fine raster tiles includes samples that are actually covered by the small primitive.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: November 15, 2016
    Assignee: NVIDIA Corporation
    Inventors: Eric Lum, Walter R. Steiner, Justin Cobb
  • Patent number: 9483270
    Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed tiled caching. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: November 1, 2016
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner
  • Patent number: 9311733
    Abstract: One embodiment of the present invention sets forth a technique for improved rasterization of round points mapped into a tile space within a graphics processing pipeline. A set of candidate tiles are selected based on proximity to a round point. A tile within the set of candidate tiles may be rejected based on a rejection boundary. A tile may be rejected if no vertex associated with the tile is within the coverage area. Performance is improved by rejecting certain unneeded tiles that would otherwise be included in conventional rasterization. One embodiment advantageously enlists line drawing circuitry to determine whether a given tile intersects the coverage area.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 12, 2016
    Assignee: NVIDIA Corporation
    Inventors: Walter R. Steiner, Eric B. Lum
  • Patent number: 8933933
    Abstract: One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: January 13, 2015
    Assignee: NVIDIA Corporation
    Inventors: Mark J. French, Emmett M. Kilgariff, Steven E. Molnar, Walter R. Steiner, Douglas A. Voorhies, Adam Clark Weitkemper
  • Patent number: 8928676
    Abstract: In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: January 6, 2015
    Assignee: Nvidia Corporation
    Inventors: Walter R. Steiner, Franklin C. Crow, Craig M. Wittenbrink, Roger L. Allen, Douglas A. Voorhies
  • Publication number: 20140267382
    Abstract: One embodiment of the present invention sets forth a technique for improved rasterization of round points mapped into a tile space within a graphics processing pipeline. A set of candidate tiles are selected based on proximity to a round point. A tile within the set of candidate tiles may be rejected based on a rejection boundary. A tile may be rejected if no vertex associated with the tile is within the coverage area. Performance is improved by rejecting certain unneeded tiles that would otherwise be included in conventional rasterization. One embodiment advantageously enlists line drawing circuitry to determine whether a given tile intersects the coverage area.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Walter R. STEINER, Eric B. LUM
  • Publication number: 20140253555
    Abstract: A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes—a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, John S. MONTRYM, Walter R. STEINER, Justin COBB, Henry Packard MORETON
  • Publication number: 20140118364
    Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed cache tiling. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.
    Type: Application
    Filed: October 18, 2013
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad S. HAKURA, Cynthia Ann Edgeworth ALLISON, Dale L. KIRKLAND, Walter R. STEINER
  • Publication number: 20140118380
    Abstract: One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.
    Type: Application
    Filed: September 3, 2013
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad S. HAKURA, Pierre SOUILLOT, Cynthia Ann Edgeworth ALLISON, Dale L. KIRKLAND, Walter R. STEINER
  • Publication number: 20140118361
    Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed tiled caching. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.
    Type: Application
    Filed: October 18, 2013
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad S. HAKURA, Cynthia Ann Edgeworth ALLISON, Dale L. KIRKLAND, Walter R. STEINER
  • Publication number: 20140118376
    Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.
    Type: Application
    Filed: October 4, 2013
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad S. HAKURA, Walter R. STEINER, Cynthia Ann Edgeworth ALLISON, Rouslan DIMITROV, Karim M. ABDALLA, Dale L. KIRKLAND, Emmett M. KILGARIFF
  • Publication number: 20130342547
    Abstract: A technique for early sample evaluation during coarse rasterization of primitives reduces the number of pixel tiles that are processed during fine rasterization of the primitive. A primitive bounding box determines when a primitive is small and may not actually cover any samples within at least one fine raster tile. Early sample evaluation is performed for the small primitive during coarse rasterization and the small primitive is discarded when no samples are actually covered by the small primitive. When the small primitive lies on a boundary between at least two fine raster tiles, early sample evaluation is performed during coarse rasterization to correctly identify which, if any, of the at least two fine raster tiles includes samples that are actually covered by the small primitive.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Inventors: Eric LUM, Walter R. STEINER, Justin COBB
  • Patent number: 8537168
    Abstract: A method and system for deferred coverage mask generation in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and performing a bounding box test on the graphics primitive to define a bounding rectangle for the graphics primitive. A combined coverage mask is then generated after the completion of the bounding box test. The combined coverage mask indicates a plurality of pixels that are covered by the graphics primitive. The combined coverage mask is divided into a plurality of sub-portions. The sub-portions are allocated to a plurality of raster components to determine sub-pixel coverage for the sub-portions.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: September 17, 2013
    Assignee: NVIDIA Corporation
    Inventors: Walter R. Steiner, Jeffrey R. Sewall
  • Publication number: 20130187956
    Abstract: In a graphics processing pipeline, a processing unit establishes a bounding box around a polygon in order to identify sample points that are covered by the polygon. For a given sample point included within the bounding box, the processing unit constructs a set of lines that intersect at the sample point, where each line in the set of lines is parallel to at least one side of the polygon. When all vertices of the polygon reside on one side of at least one line in the set of lines, the processing unit may reduce the size of the bounding box to exclude the sample point.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Inventors: Walter R. STEINER, Eric LUM, Dale L. KIRKLAND, Steven James HEINRICH, David Charles PATRICK
  • Publication number: 20070296725
    Abstract: In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.
    Type: Application
    Filed: June 23, 2006
    Publication date: December 27, 2007
    Inventors: Walter R. Steiner, Franklin C. Crow, Craig M. Wittenbrink, Roger L. Allen, Douglas A. Voorhies