Patents by Inventor Walter Schwarzenbach

Walter Schwarzenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210118936
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventor: Walter Schwarzenbach
  • Patent number: 10957577
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 23, 2021
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 10903263
    Abstract: A front-side type image sensor includes a substrate successively comprising a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P? type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 26, 2021
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Publication number: 20200321243
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: October 8, 2020
    Applicants: Soitec, Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Publication number: 20200295138
    Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0?x?1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.
    Type: Application
    Filed: March 31, 2017
    Publication date: September 17, 2020
    Inventors: Christophe Figuet, Ludovic Ecarnot, Bich-Yen Nguyen, Walter Schwarzenbach, Daniel Delprat, Ionut Radu
  • Patent number: 10672646
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 2, 2020
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Publication number: 20200152689
    Abstract: A semiconductor on insulator type structure, which may be sued for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.
    Type: Application
    Filed: March 21, 2018
    Publication date: May 14, 2020
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot
  • Publication number: 20200127041
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and/or metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Application
    Filed: January 10, 2018
    Publication date: April 23, 2020
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Publication number: 20190348462
    Abstract: A substrate for a front-side-type image sensor includes, successively, a supporting semiconductor substrate, an electrically insulating layer, and a semiconductor layer, known as the active layer. The active layer is an epitaxial layer of silicon-germanium having a germanium content of less than 10%. The disclosure also relates to a method for the production of such a substrate.
    Type: Application
    Filed: January 10, 2018
    Publication date: November 14, 2019
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Publication number: 20190267425
    Abstract: A front-side type image sensor, includes a substrate successively comprising a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P? type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.
    Type: Application
    Filed: October 10, 2017
    Publication date: August 29, 2019
    Inventor: Walter Schwarzenbach
  • Publication number: 20190181035
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.
    Type: Application
    Filed: May 17, 2017
    Publication date: June 13, 2019
    Applicant: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 9698063
    Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: July 4, 2017
    Assignee: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
  • Patent number: 9576798
    Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: February 21, 2017
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Walter Schwarzenbach, Christophe Maleville
  • Publication number: 20160086803
    Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: November 6, 2015
    Publication date: March 24, 2016
    Inventors: Bich-Yen Nguyen, Walter Schwarzenbach, Christophe Maleville
  • Patent number: 9209301
    Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: December 8, 2015
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Walter Schwarzenbach, Christophe Maleville
  • Patent number: 9190284
    Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thic
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 17, 2015
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Carine Duret, Francois Boedt
  • Publication number: 20150118764
    Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising: measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thi
    Type: Application
    Filed: May 1, 2013
    Publication date: April 30, 2015
    Inventors: Walter Schwarzenbach, Carine Duret, Francois Boedt
  • Publication number: 20150014822
    Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Application
    Filed: February 18, 2013
    Publication date: January 15, 2015
    Applicant: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
  • Patent number: 8728913
    Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 20, 2014
    Assignee: Soitec
    Inventors: Sébastien Kerdiles, Walter Schwarzenbach, Aziz Alami-Idrissi
  • Patent number: 8617962
    Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 31, 2013
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sebastien Kerdiles