Patents by Inventor Walter Schwarzenbach

Walter Schwarzenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145314
    Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Inventors: Walter Schwarzenbach, Ludovic Ecarnot, Nicolas Daval, Bich-Yen Nguyen, Guillaume Besnard
  • Patent number: 11876020
    Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 16, 2024
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Ludovic Ecarnot, Nicolas Daval, Bich-Yen Nguyen, Guillaume Besnard
  • Patent number: 11855120
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 26, 2023
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Publication number: 20230386896
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Application
    Filed: August 14, 2023
    Publication date: November 30, 2023
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Publication number: 20230317496
    Abstract: A carrier substrate comprises monocrystalline silicon, and has a front face and a back face. The carrier substrate comprises: a surface region extending from the front face to a depth of between 800 nm and 2 microns, having less than 10 crystal-originated particles (COPs) (as detected by inspecting the surface using dark-field reflection microscopy); an upper region extending from the front face to a depth of between a few microns and 40 microns and having an interstitial oxygen (Oi) content less than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm, and a lower region extending between the upper region and the back face and having a micro-defect (BMD) concentration greater than or equal to 1E8/cm3. A method is used to manufacture such a carrier substrate.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 5, 2023
    Inventors: Isabelle Bertrand, Frédéric Alibert, Romain Bouveyron, Walter Schwarzenbach
  • Patent number: 11728207
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 15, 2023
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Publication number: 20230215760
    Abstract: A method for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications, comprises: providing a P-doped semiconductor donor substrate; forming a sacrificial layer on the donor substrate; implanting atomic species through the sacrificial layer so as to form in the donor substrate an area of embrittlement defining a thin semiconductor layer that is to be transferred; removing the sacrificial layer from the donor substrate after the implantation; providing a supporting semiconductor substrate having an electrical resistivity greater than or equal to 500 ?·cm; forming an electrically insulating layer on the supporting substrate; bonding the donor substrate on the supporting substrate, the thin semiconductor layer and the electrically insulating layer being at the interface of the bonding; detaching the donor substrate along the area of embrittlement so as to transfer the thin semiconductor layer from the donor substrate onto the supporting substrate.
    Type: Application
    Filed: May 18, 2021
    Publication date: July 6, 2023
    Inventors: Isabelle Bertrand, Walter Schwarzenbach, Frédéric Allibert
  • Publication number: 20230207382
    Abstract: A method for fabricating a semiconductor-on-insulator substrate for radiofrequency applications, comprises: forming a donor substrate through epitaxial growth of an undoped semiconductor layer on a p-doped semiconductor seed substrate; forming an electrically insulating layer on the undoped epitaxial semiconductor, implanting ion species through the electrically insulating layer, so as to form, in the undoped epitaxial semiconductor layer, a weakened area defining a semiconductor thin layer to be transferred, providing a semiconductor carrier substrate having an electrical resistivity greater than or equal to 500 ?·cm, bonding the donor substrate to the carrier substrate via the electrically insulating layer, and detaching the donor substrate along the weakened area of embrittlement so as to transfer the semiconductor thin layer from the donor substrate to the carrier substrate.
    Type: Application
    Filed: May 18, 2021
    Publication date: June 29, 2023
    Inventors: Isabelle Bertrand, Walter Schwarzenbach, Frédéric Allibert
  • Publication number: 20230127950
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventor: Walter Schwarzenbach
  • Publication number: 20230063362
    Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.
    Type: Application
    Filed: October 17, 2022
    Publication date: March 2, 2023
    Inventor: Walter Schwarzenbach
  • Publication number: 20230039295
    Abstract: A method for fabricating an image sensor, comprising: providing a receiver substrate comprising a base substrate and an active layer comprising pixels, each pixel comprising a doped region for collecting the electric charges generated in the pixel, the receiver substrate being devoid of metal interconnections, providing a donor substrate comprising a weakened zone limiting a monocrystalline semiconductor layer, bonding the donor substrate to the receiver substrate, detaching the donor substrate along the weakened zone, so as to transfer the semiconductor layer to the receiver substrate, implementing a finishing treatment on the transferred monocrystalline semiconductor layer, the finishing treatment comprising (i) thinning of the transferred monocrystalline semiconductor layer by sacrificial oxidation followed by chemical etching and (ii) smoothing of the transferred monocrystalline semiconductor layer by means of at least one rapid anneal.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 9, 2023
    Inventors: Walter Schwarzenbach, David Herisson, Alain Delpy
  • Publication number: 20230032336
    Abstract: A method for bonding a first substrate and a second substrate comprises bringing the first and second substrates into contact and implementing heating of a peripheral zone of at least one of the first and second substrates. The heating is initiated before the substrates are brought into contact and continued at least until the substrates are brought into contact in the zone. The heating is implemented by an infrared lamp configured to emit radiation having an outer boundary corresponding to the edge of the substrates.
    Type: Application
    Filed: November 24, 2020
    Publication date: February 2, 2023
    Inventors: Walter Schwarzenbach, Laurent Viravaux
  • Patent number: 11552123
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Publication number: 20220399441
    Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about ?0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon on insulator device.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 15, 2022
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, Gong Xiao, Aaron Thean, Chen Sun, Haiwen Xu
  • Patent number: 11476153
    Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: October 18, 2022
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Publication number: 20220157882
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 19, 2022
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Patent number: 11282889
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: March 22, 2022
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Publication number: 20220076993
    Abstract: The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 ?·cm and 30 k?·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: March 10, 2022
    Inventors: Yvan Morandini, Walter Schwarzenbach, Frédéric Allibert, Eric Desbonnets, Bich-Yen Nguyen
  • Publication number: 20220076992
    Abstract: A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 ?·cm and 30 k?·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region.
    Type: Application
    Filed: December 23, 2019
    Publication date: March 10, 2022
    Applicant: Soitec
    Inventors: Yvan Morandini, Walter Schwarzenbach, Frédéric Allibert, Eric Desbonnets, Bich-Yen Nguyen
  • Publication number: 20220059603
    Abstract: A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: February 24, 2022
    Inventors: Walter Schwarzenbach, Ludovic Ecarnot, Damien Massy, Nadia Ben Mohamed, Nicolas Daval, Christophe Girard, Christophe Maleville