Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thic

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising: measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thi

Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.

Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.

Abstract: The invention relates to a method of forming a structure comprising a thin layer of semiconductor material transferred from a donor substrate onto a second substrate, wherein two different atomic species are co-implanted under certain conditions into the donor substrate so as to create a weakened zone delimiting the thin layer to be transferred. The two different atomic species are implanted so that their peaks have an offset of less than 200 ? in the donor substrate, and the substrates are bonded together after roughening at least one of the bonding surfaces.

Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises: routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: A method of detaching two substrates at the embrittlement zone situated at a given depth of one of the two substrates. The method includes a separation annealing step implemented in a furnace, wherein the annealing includes a first phase during which the temperature changes along an upgrade allowing a high temperature to be reached and annealing at this high temperature to be stabilized, and a second phase during which the temperature changes along a downgrade, at the end of which the furnace is opened to unload the substrates from the furnace. The second phase is regulated so as to minimize temperature inhomogeneities such as cleavage defects at the detached surfaces of the substrates when the furnace is opened.

Abstract: The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.

Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.