Patents by Inventor Wan-don Kim

Wan-don Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7842581
    Abstract: When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor using the same. Between forming the conductive layer and the metal layer, and between forming the metal layer and the conductive layer, a cycle of supplying a metal source, purging, supplying an oxygen source, purging, plasma processing of reduction gas and purging is repeated at least once. In this case, the metal layer is formed by repeating a cycle of supplying a metal source, purging, supplying an oxygen source and purging.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Jin Chung, Jin-Yong Kim, Wan-Don Kim, Kwang-Hee Lee, Cha-Young Yoo
  • Patent number: 7781819
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jin-yong Kim, Yong-suk Tak, Jung-hee Chung, Ki-chul Kim, Oh-seong Kwon
  • Publication number: 20100209595
    Abstract: In a method of forming a strontium ruthenate thin film using water vapor as an oxidizing agent, a strontium source and a ruthenium source are used. The strontium source includes a cyclopentadienyl (Cp) ligand, an alkoxide ligand, an alkyl ligand, an amide ligand or a halide ligand, and the ruthenium source includes a beta diketonate ligand.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 19, 2010
    Inventors: Oh-Seong Kwon, Kyu-Ho Cho, Jung-Hee Chung, Jin-Yong Kim, Wan-Don Kim, Youn-Soo Kim, Yong-Suk Tak
  • Publication number: 20100200950
    Abstract: A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
    Type: Application
    Filed: September 1, 2009
    Publication date: August 12, 2010
    Inventors: Youn-soo Kim, Jae-hyoung Choi, Kyu-ho Cho, Wan-don Kim, Jae-soon Lim, Sang-yeol Kang
  • Publication number: 20100196592
    Abstract: In a method of fabricating a capacitor, a lower electrode is formed, and a dielectric layer is formed on the lower electrode. An upper electrode is foamed on the dielectric layer opposite the lower electrode. A low-temperature capping layer is formed on the upper electrode at a temperature of less than about 300° C. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 5, 2010
    Inventors: Wan-Don Kim, Kyu-Ho Cho, Jin-Yong Kim, Jae-Hyoung Choi, Jae-Soon Lim, Oh-Seong Kwon, Beom-Seok Kim, Yong-Suk Tak
  • Patent number: 7700454
    Abstract: A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jae-hyun Joo, Seok-jun Won, Jung-hee Chung, Jin-yong Kim, Suk-jin Chung
  • Publication number: 20090258470
    Abstract: Methods of manufacturing a semiconductor device include forming an absorption layer on a surface of a substrate by exposing the surface of the substrate to a first reaction gas at a first temperature. A metal oxide layer is then formed on the surface of the substrate by exposing the absorption layer to a second reaction gas at a second temperature. The first reaction gas may include a precursor containing zirconium (e.g., tetrakis(ethylmethylamino)zirconium) and the second reaction gas may include an oxidizing agent.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 15, 2009
    Inventors: Jae-Hyoung Choi, Jin-Hyuk Choi, Cha-Young Yoo, Kyu-Ho Cho, Wan-Don Kim, Kyoung-Ryul Yoon, Jae-Hyun Yeo, Yong-Suk Tak
  • Publication number: 20090130457
    Abstract: A dielectric structure includes a first dielectric layer, a buffer oxide layer and a second dielectric layer. The lower dielectric layer has a material having a perovskite structure including titanium and is formed on a substrate. The buffer oxide layer is formed on the first dielectric layer. The second dielectric layer has a perovskite structure including titanium and is formed on the buffer oxide layer.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 21, 2009
    Inventors: Wan-Don Kim, Jae-Hyoung Choi, Kyu-Ho Cho, Jung-Hee Chung, Jin-Yong Kim, Yong-Suk Tak
  • Publication number: 20090072350
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.
    Type: Application
    Filed: November 13, 2008
    Publication date: March 19, 2009
    Inventors: Wan-don Kim, Jin-yong Kim, Yong-suk Tak, Jung-hee Chung, Ki-chul Kim, Oh-seong Kwon
  • Publication number: 20090072349
    Abstract: Example embodiments provide a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may include a lower electrode including a first lower electrode and a second lower electrode, and the second lower electrode may be formed on at least a part of the first lower electrode using a material different from the first lower electrode. A dielectric film may be formed on at least a part of the second lower electrode and a first upper electrode may be formed on the dielectric film.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 19, 2009
    Inventors: Yong-Suk Tak, Jung-Hee Chung, Jin-Yong Kim, Wan-Don Kim, Young-Sun Kim
  • Patent number: 7416904
    Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Cha-Young Yoo, Suk-Jin Chung, Wan-Don Kim
  • Patent number: 7335550
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: February 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Wan-don Kim, Cha-young Yoo, Suk-jin Chung
  • Publication number: 20070207587
    Abstract: Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming the lower electrode. A capacitor dielectric layer is formed on the lower electrode and an upper electrode of the capacitor is formed on the capacitor dielectric layer.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 6, 2007
    Inventors: Wan-Don Kim, Cha-Young Yoo, Suk-Jin Chung, Jin-Yong Kim
  • Publication number: 20070167006
    Abstract: When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor using the same. Between forming the conductive layer and the metal layer, and between forming the metal layer and the conductive layer, a cycle of supplying a metal source, purging, supplying an oxygen source, purging, plasma processing of reduction gas and purging is repeated at least once. In this case, the metal layer is formed by repeating a cycle of supplying a metal source, purging, supplying an oxygen source and purging.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 19, 2007
    Inventors: Suk-Jin Chung, Jin-Yong Kim, Wan-Don Kim, Kwang-Hee Lee, Cha-Young Yoo
  • Publication number: 20070099419
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Application
    Filed: December 19, 2006
    Publication date: May 3, 2007
    Inventors: Jae-hyoung Choi, Wan-don Kim, Cha-young Yoo, Suk-jin Chung
  • Patent number: 7172946
    Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: February 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Wan-don Kim, Cha-young Yoo, Suk-jin Chung
  • Publication number: 20060263977
    Abstract: A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
    Type: Application
    Filed: August 3, 2006
    Publication date: November 23, 2006
    Inventors: Wan-don Kim, Jae-hyun Joo, Seok-jun Won, Jung-hee Chung, Jin-yong Kim, Suk-jin Chung
  • Patent number: 7091102
    Abstract: An integrated circuit device is formed by providing a substrate and forming a capacitor on the substrate. The capacitor includes a lower electrode disposed on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric. A hydrogen barrier insulation layer is formed on the upper electrode and a hydrogen barrier spacer is formed on a sidewall of the capacitor.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 15, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-jin Lim, Kwang-hee Lee, Suk-jin Chung, Cha-young Yoo, Wan-don Kim, Jin-il Lee
  • Publication number: 20060148193
    Abstract: Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).
    Type: Application
    Filed: March 13, 2006
    Publication date: July 6, 2006
    Inventors: Kwang-hee Lee, Cha-young Yoo, Han-Jin Lim, Sung-tae Kim, Suk-jin Chung, Wan-don Kim, Jung-hee Chung, Jin-il Lee
  • Publication number: 20060138511
    Abstract: Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.
    Type: Application
    Filed: February 23, 2006
    Publication date: June 29, 2006
    Inventors: Suk-jin Chung, Wan-don Kim, Cha-young Yoo, Kwang-hee Lee, Han-jin Lim, Jin-il Lee