Abstract: A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C.

Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

Abstract: A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.

Abstract: Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.

Abstract: Methods for forming a stacked capacitor include forming a first dielectric layer having a contact plug therein on an integrated circuit substrate. A second dielectric layer including a storage node hole is formed adjacent the contact plug on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer has an associated work function. The conductive layer is oxidized to form a conductive oxide layer on the conductive layer. The conductive oxide layer has an associated work function that is sufficiently close to the work function of the conductive layer that the conductive layer and the conductive oxide layer operate together as the node of the stacked capacitor. The second dielectric layer is removed to define the node of the stacked capacitor.

Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device having an upper and lower electrode formed of metal is provided. Portions of a conductive layer for a lower electrode on inner walls of holes are not removed. Portions of the conductive layer for a lower electrode outside the holes are selectively etched back and node-separated.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.

Abstract: Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.

Abstract: A fabrication method for forming a semiconductor device having a MIM (Metal-Insulator-Metal) capacitor is provided. A lower electrode is formed on a substrate. The lower electrode is subjected to a pre-annealing. The pre-annealing includes a thermal annealing in a hydrogen atmosphere, a nitrogen atmosphere or a mixed atmosphere of hydrogen and nitrogen. A capacitor dielectric layer is formed on the lower electrode. An upper electrode is formed on the capacitor dielectric layer. According to the present invention, the characteristic of a MIM capacitor can be enhanced by the pre-annealing without any substantial change in the materiality of the lower electrode.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

Abstract: Methods are provided for manufacturing an integrated circuit device in which a metal layer is formed on an integrated circuit substrate. A capping layer is formed on the metal layer opposite the integrated circuit substrate. The metal layer covered with the capping layer is heat-treated. The capping layer is removed and the metal layer, which is exposed by removal of the capping layer, is plasma-treated.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

Abstract: A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C.

Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: A method for fabricating a semiconductor device using a high dielectric material as a dielectric film of a capacitor wherein an etch stopping layer such as BST having a good dry etch selectivity with respect to an interlayer insulating film is formed on the adhesion layer formed on an upper electrode. This etch stopping layer prevents the upper electrode of a capacitor from being exposed to be etched during forming a metal contact.