Abstract: A method of operating a controller includes sensing power-on of a memory system including a semiconductor memory device, determining whether to delay a garbage collection operation performed during an initial operation of the memory system, based on a sudden-power off (SPO) count value, and controlling the semiconductor memory device to perform the garbage collection operation based on the determination result.

Abstract: A transceiver includes a first mixer, a noise reduction circuit, a first amplifier, a second amplifier and an input/output (I/O) port. The first mixer receives first data and a first clock signal, and generates a first signal to be transmitted to an external device based on the first data and the first clock signal. The noise reduction circuit provides the first clock signal to the first mixer. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from the external device. The I/O port is shared by the first amplifier and the second amplifier, and is configured to output the amplified first signal and receive the second signal. The noise reduction circuit activates the first clock signal during an activation time interval for the first data, and deactivates the first clock signal during a deactivation time interval for the first data.

Abstract: An electronic device includes a feedback oscillator configured to output a first oscillation signal and a second oscillation signal, the second oscillation signal having a defined phase difference from the first oscillation signal, the feedback oscillator including a phase shifter configured to receive the first oscillation signal and output the second oscillation signal, an up-conversion mixer configured to output a first loopback signal obtained by mixing the first oscillation signal with a reference tone signal, and output a second loopback signal obtained by mixing the second oscillation signal with the reference tone signal, and a receiver configured to generate a first reference IQ signal from the first loopback signal, generate a second reference IQ signal from the second loopback signal, and compare an actual phase difference between the first reference IQ signal and the second reference IQ signal with the defined phase difference.

Abstract: A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

Abstract: An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

Abstract: An electronic device includes a feedback oscillator configured to output a first oscillation signal and a second oscillation signal, the second oscillation signal having a defined phase difference from the first oscillation signal, the feedback oscillator including a phase shifter configured to receive the first oscillation signal and output the second oscillation signal, an up-conversion mixer configured to output a first loopback signal obtained by mixing the first oscillation signal with a reference tone signal, and output a second loopback signal obtained by mixing the second oscillation signal with the reference tone signal, and a receiver configured to generate a first reference IQ signal from the first loopback signal, generate a second reference IQ signal from the second loopback signal, and compare an actual phase difference between the first reference IQ signal and the second reference IQ signal with the defined phase difference.

Abstract: A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.

Abstract: The present disclosure relates to a complex concentrated soft magnetic amorphous alloy with multi-complex quenched-in nuclei and a method for manufacturing the same, and more specifically, to a complex concentrated soft magnetic amorphous alloy which exhibits low coercivity while improving glass forming ability through the design of configurational entropy control complex alloying composition of a first main element group (Fe, Co, Ni), which determines the degree of magnetization as ferromagnetic metallic elements, a second alloying element group (B, Si, P, C), which facilitates amorphous formation, and a third cluster element group (Ca, Cu, Ag), which forms multi-complex quenched-in nuclei, and a method for manufacturing the same. The complex concentrated soft magnetic amorphous alloy developed in the present disclosure is characterized by having an excellent switching effect in which the alloy is easily magnetized and demagnetized when a magnetic field is applied and removed by implementing low coercivity.

Abstract: A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

Abstract: A method of operating a controller includes sensing power-on of a memory system including a semiconductor memory device, determining whether to delay a garbage collection operation performed during an initial operation of the memory system, based on a sudden-power off (SPO) count value, and controlling the semiconductor memory device to perform the garbage collection operation based on the determination result.

Abstract: A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

Abstract: A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

Abstract: An electronic device includes a feedback oscillator configured to output a first oscillation signal and a second oscillation signal, the second oscillation signal having a defined phase difference from the first oscillation signal, the feedback oscillator including a phase shifter configured to receive the first oscillation signal and output the second oscillation signal, an up-conversion mixer configured to output a first loopback signal obtained by mixing the first oscillation signal with a reference tone signal, and output a second loopback signal obtained by mixing the second oscillation signal with the reference tone signal, and a receiver configured to generate a first reference IQ signal from the first loopback signal, generate a second reference IQ signal from the second loopback signal, and compare an actual phase difference between the first reference IQ signal and the second reference IQ signal with the defined phase difference.

Abstract: Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.

Abstract: A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.

Abstract: A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

Abstract: Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.

Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Abstract: A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

Abstract: A radio frequency (RF) transmitter including a switched-capacitor digital-to-analog converter (SC-DAC) configured to selectively generate a first RF output signal having a first output power control range or a second RF output signal having a second output power control range from input signals received through a plurality of lines may be provided.