Abstract: A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.

Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

Abstract: A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.

Abstract: In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. The channel layer may pass through the interlayer insulating layers and the conductive patterns. The cell blocking insulating layers may be respectively arranged between the channel layer and the conductive patterns. The dummy blocking insulating layers may be respectively arranged between the channel layer and the interlayer insulating layers, and may protrude further toward a side wall of the channel layer than the cell blocking insulating layers. The data storage layer may surround the side wall of the channel layer, and may be formed on a concavo-convex structure defined by the cell blocking insulating layers and the dummy blocking insulating layers.

Abstract: A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Abstract: In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. The channel layer may pass through the interlayer insulating layers and the conductive patterns. The cell blocking insulating layers may be respectively arranged between the channel layer and the conductive patterns. The dummy blocking insulating layers may be respectively arranged between the channel layer and the interlayer insulating layers, and may protrude further toward a side wall of the channel layer than the cell blocking insulating layers. The data storage layer may surround the side wall of the channel layer, and may be formed on a concavo-convex structure defined by the cell blocking insulating layers and the dummy blocking insulating layers.

Abstract: In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. The channel layer may pass through the interlayer insulating layers and the conductive patterns. The cell blocking insulating layers may be respectively arranged between the channel layer and the conductive patterns. The dummy blocking insulating layers may be respectively arranged between the channel layer and the interlayer insulating layers, and may protrude further toward a side wall of the channel layer than the cell blocking insulating layers. The data storage layer may surround the side wall of the channel layer, and may be formed on a concavo-convex structure defined by the cell blocking insulating layers and the dummy blocking insulating layers.

Abstract: A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Abstract: A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Abstract: In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. The channel layer may pass through the interlayer insulating layers and the conductive patterns. The cell blocking insulating layers may be respectively arranged between the channel layer and the conductive patterns. The dummy blocking insulating layers may be respectively arranged between the channel layer and the interlayer insulating layers, and may protrude further toward a side wall of the channel layer than the cell blocking insulating layers. The data storage layer may surround the side wall of the channel layer, and may be formed on a concavo-convex structure defined by the cell blocking insulating layers and the dummy blocking insulating layers.

Abstract: A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Abstract: A method of forming gate patterns of a nonvolatile memory device comprises forming stack patterns each having an insulating layer and a conductive layer stacked over a semiconductor substrate, and forming an anti-oxidation layer on sidewalls of the insulating layer by selectively nitrifying the insulating layer.

Abstract: A method of forming gate patterns of a nonvolatile memory device comprises forming stack patterns each having an insulating layer and a conductive layer stacked over a semiconductor substrate, and forming an anti-oxidation layer on sidewalls of the insulating layer by selectively nitrifying the insulating layer.

Abstract: The present invention relates to a method of forming isolation layers of a semiconductor memory device. According to a method of forming isolation layers of a semiconductor memory device in accordance with an aspect of the present invention, a tunnel dielectric layer, a conductive layer for a floating gate, a buffer oxide layer, and a pad nitride layer are sequentially formed over a semiconductor substrate. A trench is formed by selectively etching the pad nitride layer, the buffer oxide layer, the conductive layer for the floating gate, the tunnel dielectric layer, and the semiconductor substrate. The trench is gap-filled by forming a dielectric layer over the entire structure including the trench. A curing process is performed using a pre-heated curing gas. A height of the isolation layers is controlled by performing a cleaning process.

Abstract: A method of forming an isolation layer of a semiconductor device is provided. A wafer having a polysilizane (PSZ) layer formed is loaded into a chamber while a loading temperature is maintained in the chamber. An oxygen gas is supplied to the chamber. After the loading, a temperature within the chamber is raised up to a process temperature. Subsequently, the PSZ layer is cured in the chamber maintaining the process temperature. During the curing step, vapor is supplied to the chamber such that a ratio of the oxygen gas and the vapor is set in the range of 1:1 to 50:1. The inside of the chamber is purged by supplying an inert gas to the chamber where the oxygen gas and the vapor are blocked to be supplied.

Abstract: A method of forming an oxide layer in a semiconductor device comprising the step of loading a semiconductor substrate in a chamber, optionally increasing a temperature of an interior of the chamber, performing the first oxidation process in the chamber under the atmosphere of ozone to form an oxide layer on the semiconductor substrate, and lowering a temperature of an interior of the chamber.