Abstract: A semiconductor device includes a first integrated circuit, a bridge die, and a redistribution layer (RDL) structure. The first integrated circuit includes a first interconnect structure, a first passivation layer and a first conductive connector electrically connected to the first interconnect structure and disposed on the first passivation layer. The bridge die bridge die includes a second interconnect structure, a second passivation layer and a second conductive connector electrically connected to the second interconnect structure. The RDL structure is disposed between and electrically connected to the first integrated circuit and the bridge die, wherein the first passivation layer is in direct contact with the first conductive connector, the first conductive connector is in direct contact with the RDL structure, and the first passivation layer is a single layer and includes a first inorganic material.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, and wherein the breakdown voltage enhancement and leakage prevention structure comprises a reduced surface field (RESURF) structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a reduced surface field (RESURF) structure, forming a source in the epitaxial layer and a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact on the opposing side of the epitaxial layer from the source contact.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: In a micro-electromechanical system (MEMS) structure, at least one chemical stop structure is formed to reduce inadvertent etching of adhesion layers. A first adhesion layer and a second adhesion layer are separated by a primary dielectric layer. The primary dielectric layer includes a recess that forms a stair. The second adhesion layer includes an annular opening, and a protective material covers the sides of the second adhesion layer in the annular opening. A base plate layer covers the second adhesion layer and fills the recess and the annular opening. An annular via passes through the base plate layer and the protective material down to the primary dielectric layer. The protective material and the base plate layer each act as chemical stop structures that separate the first adhesion layer from the second adhesion layer.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: Certain embodiments of the present disclosure provide techniques training a user detection model to identify a user of a software application based on voice recognition. The method generally includes receiving a data set including a plurality of voice interactions with users of a software application. For each respective recording in the data set, a spectrogram representation is generated based on the respective recording. A plurality of voice recognition models are trained. Each of the plurality of voice recognition models is trained based on the spectrogram representation for each of the plurality of voice recordings in the data set. The plurality of voice recognition models are deployed to an interactive voice response system.

Abstract: Provided are a compound represented by Formula 1, an organic electric element including a first electrode, a second electrode, and an organic material layer between the first electrode and the second electrode, and an electronic device thereof, wherein the compound represented by Formula 1 is included in the organic material layer, thereby the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time can be improved.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A method includes forming a metal pad, depositing a passivation layer on the metal pad, and planarizing the passivation layer, so that the passivation layer includes a planar top surface. The method further includes etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed to the opening, and forming a conductive via including a lower portion in the opening, and an upper portion higher than the passivation layer. A polymer layer is then dispensed to cover the conductive via.

Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate and surrounding the gate structure, a contact extending in the dielectric layer to the substrate, a protection layer surrounding a portion of the contact embedded in the substrate, an etch stop layer between the dielectric layer and the substrate extending from the gate structure to the contact, in which a top surface of the protection layer is lower than a top surface of the etch stop layer; and a metal alloy structure at a bottom of the contact.